參數(shù)資料
型號(hào): MAX2120
廠商: Maxim Integrated Products, Inc.
英文描述: Complete, Direct-Conversion Tuner for DVB-S and Free-to-Air Applications
中文描述: 完備的直接變頻調(diào)諧器,用于DVB-S和免費(fèi)廣播系統(tǒng)
文件頁數(shù): 18/21頁
文件大?。?/td> 316K
代理商: MAX2120
M
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
18
______________________________________________________________________________________
3-Bit ADC
The MAX2120 has an internal 3-bit ADC connected to
the VCO tune pin (VTUNE). This ADC can be used for
checking the lock status of the VCOs.
Table 14 summarizes the ADC trip points, and the VCO
lock indication. The VCO autoselect routine will only
select a VCO in the “VAS locked” range. This allows
room for a VCO to drift over temperature and remain in
a valid “l(fā)ocked” range.
The ADC must first be enabled by setting the ADE bit in
the VCO register. The ADC reading is latched by a sub-
sequent programming of the ADC latch bit (ADL = 1).
The ADC value is reported in the Status Byte-2 register
(see Table 13).
Power-Down and Standby Modes
The MAX2120 features normal operating mode, power-
down mode, and standby mode using the I
2
C interface.
Setting a logic-high to the PWDN bit in the Control regis-
ter enables power-down. In this mode, all circuitries
except for the 2-wire-compatible bus are disabled, allow-
ing for programming of the MAX2120 registers while in
power-down.
Setting a logic-high to the STBY bit in the Control register
puts the device into standby mode, during which only the
2-wire-compatible bus, the crystal oscillator, the XTAL
buffer, and the XTAL buffer divider are active.
In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active mode.
Default register values are provided for the user’s conve-
nience only. It’s the user’s responsibility to load all the
registers no sooner than 100μs after the device is pow-
ered up. The various power-down modes are summa-
rized in Table 15.
Layout Considerations
The MAX2120 EV kit serves as a guide for PCB
layout. Keep RF signal lines as short as possible to mini-
mize losses and radiation. Use controlled impedance on
all high-frequency traces. For proper operation, the
exposed paddle must be soldered evenly to the board’s
ground plane. Use abundant vias beneath the exposed
paddle for maximum heat dissipation. Use abundant
ground vias between RF traces to minimize undesired
coupling. Bypass each V
CC
pin to ground with a 1nF
capacitor placed as close as possible to the pin.
ADC[2:0]
000
001
010
101
110
111
LOCK STATUS
Out of Lock
Locked
VAS Locked
VAS Locked
Locked
Out of Lock
Table 14. ADC Trip Points and Lock Status
Table 15. Power-Down Modes
POWER-DOWN CONTROL
MODE
PWDN BIT
CIRCUIT STATES
STBY BIT
SIGNAL
PATH
2-WIRE
INTERFACE
XTAL
DESCRIPTION
Normal
Power-Down
0
1
0
0
On
Off
On
On
On
Off
All circuits active.
2-wire interface is active.
Standby
0
1
Off
On
On
2-wire interface, XTAL, and XTAL
buffer/divider are active.
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