參數(shù)資料
型號: MAX2120
廠商: Maxim Integrated Products, Inc.
英文描述: Complete, Direct-Conversion Tuner for DVB-S and Free-to-Air Applications
中文描述: 完備的直接變頻調(diào)諧器,用于DVB-S和免費廣播系統(tǒng)
文件頁數(shù): 10/21頁
文件大?。?/td> 316K
代理商: MAX2120
M
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
10
______________________________________________________________________________________
MSB
LSB
DATA BYTE
D[4]
REG
NO
REGISTER
NAME
READ/
WRITE
REG
ADDRESS
D[7]
D[6]
D[5]
D[3]
D[2]
D[1]
D[0]
1
N-Divider
MSB
Write
0x00
X
N[14]
N[13]
N[12]
N[11]
N[10]
N[9]
N[8]
2
N-Divider
LSB
Write
0x01
N[7]
N[6]
N[5]
N[4]
N[3]
N[2]
N[1]
N[0]
3
Charge
Pump
Not Used
Not Used
XTAL
Divider/
R-Divider
Write
0x02
CPMP[1]
0
X
X
CPMP[0]
0
X
X
CPLIN[1]
0
X
X
CPLIN[0]
0
X
X
X
X
X
X
4
5
Write
Write
0x03
0x04
X
X
X
X
X
X
X
X
6
Write
0x05
XD[2]
XD[1]
XD[0]
R[4]
R[3]
R[2]
R[1]
R[0]
7
PLL
Write
0x06
D24
CPS
0
VCO[3]
LP[6]
X
PLL
ICP
1
X
X
X
X
X
8
9
10
11
VCO
LPF
Control
Shutdown
Write
Write
Write
Write
0x07
0x08
0x09
0x0A
VCO[4]
LP[7]
STBY
X
VCO[2]
LP[5]
PWDN
DIV
VCO[1]
LP[4]
X
VCO
VCO[0]
LP[3]
BBG[3]
BB
VAS
LP[2]
BBG[2] BBG[1] BBG[0]
RFMIX RFVG
LD
MUX[2]
0
0
ADL
LP[1]
ADE
LP[0]
FE
LD
12
Test
Write
0x0B
CPTST[2]
0
CPTST[1]
0
CPTST[0]
0
X
TURBO
1
LD
MUX[1]
MUX[0]
0
13
Status
Byte-1
Status
Byte-2
Read
0x0C
POR
VASA
VASE
LD
X
X
X
X
14
Read
0x0D
VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
Table 1. Register Configuration
0 = Set to “0” for factory-tested operation.
1 = Set to “1” for factory-tested operation.
X = Don’t care.
Table 2. N-Divider MSB Register
BIT NAME
X
BIT LOCATION (0 = LSB)
7
DEFAULT
X
FUNCTION
Don’t care.
N[14:8]
6–0
0000011
Sets the most significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
Table 3. N-Divider LSB Register
BIT NAME
BIT LOCATION (0 = LSB)
Detailed Description
Register Description
The MAX2120 includes 12 user-programmable registers
and 2 read-only registers. See Table 1 for register con-
figurations. The register configuration of Table 1 shows
each bit name and the bit usage information for all regis-
ters. Note that all registers must be written after and no
earlier than 100μs after the device is powered up.
DEFAULT
FUNCTION
N[7:0]
7–0
10110110
Sets the least significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
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