Read Cycle
There are only two registers on the MAX2112 that are
available to be read by the master. When addressed
with a read command, the MAX2112 sends back the
contents of both read registers (Status Byte-1 and
Status Byte-2).
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a read bit (R/
W
= 1). If the slave address byte is
successfully received, the MAX2112 issues an ACK. The
master then reads the contents of the Status Byte-1 reg-
ister, beginning with the most significant bit, and
acknowledges if the byte is received successfully. Next,
the master reads the contents of the Status Byte-2 regis-
ter. At this point the master can issue an ACK or NACK
and then a STOP condition to terminate the read cycle.
Application Information
The MAX2112 downconverts RF signals in the 925MHz to
2175MHz range directly to the baseband I/Q signals. The
devices are targeted for digital DBS tuner applications.
RF Input
The RF input of the MAX2112 is internally matched to
75
Ω
. Only a DC-blocking capacitor is needed. See the
Typical Application Circuit
RF Gain Control
The MAX2112 features a variable-gain low-noise ampli-
fier providing 73dB of RF gain range. The voltage con-
trol (VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide
15dB of gain control range programmable in 1dB
steps. The VGA gain can be serially programmed
through the SPI interface by setting bits BBG[3:0] in the
Control register.
Baseband Lowpass Filter
The MAX2112 includes a programmable on-chip
7th-order Butterworth filter. The filter -3dB corner fre-
quency can be adjusted from approximately 4MHz to
40MHz by programming the LPF[7:0] register using the
following equation:
LPF[3:0]
dec
= (f
-3dB
- 4MHz) / 0.29MHz + 12,
where f
-3dB
is in units of MHz.
Total device supply current depends on the filter BW
setting. See Supply Current vs. Baseband Filter Cutoff
Frequency in the Typical Operating Characteristics for
more information.
DC Offset Cancellation
The DC offset cancellation is required to maintain the
I/Q output dynamic range. Connecting an external
capacitor between IDC+ and IDC- forms a highpass fil-
ter for the I channel and an external capacitor between
QDC+ and QDC- forms a highpass filter for the Q chan-
nel. Keep the value of the external capacitor less than
47nF to form a typical highpass corner of 250Hz.
XTAL Oscillator
The MAX2112 contains an internal reference oscillator,
reference output divider, and output buffer. All that is
required is to connect a crystal through a series 1nF
capacitor. Use a crystal with an ESR less than 60
Ω
for
a 27MHz crystal. The typical input capacitance is 16pF.
Contact the factory for more information if not using a
27MHz crystal.
VCO Autoselect (VAS)
The MAX2112 includes 24 VCOs. The local oscillator
frequency can be manually selected by programming
the VCO[4:0] bits in the VCO register. The selected VCO
is reported in the Status Byte-2 register (see Table 15).
Alternatively, the MAX2112 can be set to autonomously
choose a VCO by setting the VAS bit in the VCO regis-
ter to logic-high. The VAS routine is initiated once the
F-Divider LSB register word (REG 5) is loaded.
In the event that only the N-divider register or
F-divider MSB word is changed, the F-divider LSB
word must also be loaded last to initiate the VCO
autoselect function.
The VCO value programmed in the
VCO[4:0] register serves as the starting point for the auto-
matic VCO selection process.
During the selection process, the VASE bit in the Status
Byte-1 register is cleared to indicate the autoselection
function is active. Upon successful completion, bits VASE
and VASA are set and the VCO selected is reported in the
Status Byte-2 register (see Table 15). If the search is
unsuccessful, VASA is cleared and VASE is set. This indi-
cates that searching has ended but no good VCO has
been found, and occurs when trying to tune to a frequen-
cy outside the VCO’s specified frequency range.
M
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
______________________________________________________________________________________
15
WRITE DEVICE ADDRESS
R/
W
ACK
READ FROM STATUS BYTE-1 REGISTER
ACK
READ FROM STATUS BYTE-2 REGISTER
ACK/
NACK
START
1100000
1
—
—
—
—
—
STOP
Figure 3. Example: Receive Data from Read Registers