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參數(shù)資料
| 型號(hào)： | MAX2112 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Complete, Direct-Conversion Tuner for DVB-S2 Applications |
| 中文描述： | 完備的直接變頻調(diào)諧器，用于DVB-S2系統(tǒng) |
| 文件頁(yè)數(shù)： | 14/19頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | MAX2112 |
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M
2-Wire Serial Interface
The MAX2112 uses a 2-wire I
2
C-compatible serial inter-
face consisting of a serial-data line (SDA) and a serial-
clock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX2112 and the master
at clock frequencies up to 400kHz. The master initiates
a data transfer on the bus and generates the SCL sig-
nal to permit data transfer. The MAX2112 behaves as a
slave device that transfers and receives data to and
from the master. SDA and SCL must be pulled high
with external pullup resistors (1k
Ω
or greater) for proper
bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2112 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the START and STOP Conditionssection). Both SDA
and SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX2112 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master must reattempt
communication at a later time.
Slave Address
The MAX2112 has a 7-bit slave address that must be
sent to the device following a START condition to initi-
ate communication. The slave address is internally pro-
grammed to 1100000. The eighth bit (R/
W
) following
the 7-bit address determines whether a read or write
operation occurs.
The MAX2112 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/
W
bit (Figure 1).
Write Cycle
When addressed with a write command, the MAX2112
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/
W
= 0). The MAX2112 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to (see
Table 1 for register addresses). If the slave acknowl-
edges the address, the master can then write one byte
to the register at the specified address. Data is written
beginning with the most significant bit. The MAX2112
again issues an ACK if the data is successfully written
to the register. The master can continue to write data to
the successive internal registers with the MAX2112
acknowledging each successful transfer, or it can ter-
minate transmission by issuing a STOP condition. The
write cycle does not terminate until the master issues a
STOP condition.
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
14
______________________________________________________________________________________
SCL
1
2
3
4
5
6
7
1
1
0
0
0
0
0
8
9
R/W
ACK
SLAVE ADDRESS
S
SDA
Figure 1. MAX2112 Slave Address Byte
WRITE DEVICE
ADDRESS
R/
W
ACK
WRITE REGISTER
ADDRESS
ACK
WRITE DATA TO
REGISTER 0x00
ACK
WRITE DATA TO
REGISTER 0x01
ACK
WRITE DATA TO
REGISTER 0x02
ACK
START
1100000
0
—
0x00
—
0x0E
—
0xD8
—
0xE1
—
STOP
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX2112_10 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Complete, Direct-Conversion Tuner for DVB-S2 Applications |
| MAX2112CTI+ | 功能描述:調(diào)諧器 Direct Conv Tuner Tuner for DVB-S2 RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
| MAX2112CTI+T | 功能描述:調(diào)諧器 Direct Conv Tuner Tuner for DVB-S2 RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
| MAX2112ETI/GG8 | 制造商:Maxim Integrated Products 功能描述:COMPLETE, DIRECT-CONVERSION TUNER FOR DVB-S2 APPLICATIONS - Rail/Tube |
| MAX2112ETI+ | 功能描述:調(diào)諧器 Direct Conv Tuner Tuner for DVB-S2 RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
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