參數(shù)資料
型號(hào): MAX19706
廠商: Maxim Integrated Products, Inc.
英文描述: 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
中文描述: 10位、22Msps、超低功耗模擬前端
文件頁(yè)數(shù): 28/37頁(yè)
文件大小: 561K
代理商: MAX19706
M
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
28
______________________________________________________________________________________
The conversion requires 12 clock edges (1 for input
sampling, 1 for each of the 10 bits, and 1 at the end for
loading into the serial output register) to complete one
conversion cycle (when no averaging is being done).
Each conversion of an average (when averaging is set
greater than 1) requires 12 clock edges. The conver-
sion clock is generated from the system clock input
(CLK). An SPI-programmable divider divides the sys-
tem clock by the appropriate divisor (set with bits AD7,
AD8, and AD9; see Table 15) and provides the conver-
sion clock to the auxiliary ADC. The auxiliary ADC has a
maximum conversion rate of 333ksps. The maximum
conversion clock frequency is 4MHz (333ksps x 12
clocks). Choose the proper divider value to keep the
conversion clock frequency under 4MHz, based upon
the system CLK frequency supplied to the MAX19707
(see Table 15). The total conversion time (t
CONV
) of the
auxiliary ADC can be calculated as t
CONV
= (12 x
N
AVG
x N
DIV
) / f
CLK
; where N
AVG
is the number of
averages (see Table 14), N
DIV
is the CLK divisor (see
Table 15), and f
CLK
is the system CLK frequency.
DOUT is normally in a tri-state condition. Upon setting
the auxiliary ADC start conversion bit (bit AD0), DOUT
becomes active and goes high, indicating that the aux-
ADC is busy. When the conversion cycle is complete
(including averaging), the data is placed into an output
register and DOUT goes low, indicating that the output
data is ready to be driven onto DOUT. When bit AD10 is
set (AD10 = 1), the aux-ADC enters a data output mode
where data is available on DOUT upon the next asser-
tion low of
CS
. The auxiliary ADC data is shifted out of
DOUT (MSB first) with the data transitioning on the
falling edge of the serial clock (SCLK). DOUT enters tri-
state condition when
CS
is deasserted high. When bit
AD10 is cleared (AD10 = 0), the aux-ADC data is not
available on DOUT (see Table 16).
DIN can be written independent of DOUT state. A 16-
bit instruction at DIN updates the device configuration.
To prevent modifying internal registers while reading
data from DOUT, hold DIN at a high state. This effec-
tively writes all ones into address 1111. Since address
1111 does not exist, no internal registers are affected.
Table 14. Auxiliary ADC Averaging
Table 15. Auxiliary ADC Clock (CLK)
Divider
Table 16. Auxiliary ADC Data Output
Mode
AD10
0
SELECTION
Aux-ADC Data is Not Available on DOUT (Default)
1
Aux-ADC Enters Data Output Mode Where
Data is Available on DOUT
AD6
0
0
0
0
1
1
1
AD5
0
0
1
1
0
0
1
AD4
0
1
0
1
0
1
X
AUX-ADC AVERAGING
1 C onver si on ( N o Aver ag ng ( D efaul )
Average of 2 Conversions
Average of 4 Conversions
Average of 8 Conversions
Average of 16 Conversions
Average of 32 Conversions
Average of 32 Conversions
AD9
0
0
0
0
1
1
1
1
AD8
0
0
1
1
0
0
1
1
AD7
0
1
0
1
0
1
0
1
AUX-ADC CONVERSION CLOCK
CLK Divided by 1 (Default)
CLK Divided by 2
CLK Divided by 4
CLK Divided by 8
CLK Divided by 16
CLK Divided by 32
CLK Divided by 64
CLK Divided by 128
X = Don’t care.
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MAX19706ETM+T 功能描述:ADC / DAC多通道 22Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19706ETM-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19706EVCMOD2 功能描述:ADC / DAC多通道 Evaluation System for the MAX19706 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40