參數(shù)資料
型號： MAX19706
廠商： Maxim Integrated Products, Inc.
英文描述： 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
中文描述： 10位、22Msps、超低功耗模擬前端
文件頁數(shù)： 26/37頁
文件大?。?/td> 561K
代理商： MAX19706
M
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
26
______________________________________________________________________________________
Mode-Recovery Timing
Figure 7 shows the mode-recovery timing diagram.
t
WAKE
is the wakeup time when exiting shutdown, idle,
or standby mode and entering Rx or Tx mode. t
ENABLE
is the recovery time when switching between either Rx
or Tx mode. t
WAKE
or t
ENABLE
is the time for the Rx ADC
to settle within 1dB of specified SINAD performance and
Tx DAC settling to 10 LSB error. t
WAKE
and t
ENABLE
times are measured after either the 16-bit serial com-
mand is latched into the MAX19707 by a
CS
transition
high (SPI controlled) or a T/
R
logic transition (external
Tx-Rx control). In FAST mode, the recovery time is 0.5μs
to switch between Tx or Rx modes.
System Clock Input (CLK)
Both the Rx ADC and Tx DAC share the CLK input. The
CLK input accepts a CMOS-compatible signal level set
by OV
DD
from 1.8V to V
DD
. Since the interstage con-
version of the device depends on the repeatability of
the rising and falling edges of the external clock, use a
clock with low jitter and fast rise and fall times (< 2ns).
Specifically, sampling occurs on the rising edge of the
clock signal, requiring this edge to provide the lowest
possible jitter. Any significant clock jitter limits the SNR
performance of the on-chip Rx ADC as follows:
where f
IN
represents the analog input frequency and
t
AJ
is the time of the clock jitter.
Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX19707 clock input operates
with an OV
DD
/ 2 voltage threshold and accepts a 50%
±15% duty cycle.
log
SNR
f
IN
t
=
×
×
×
×
20
1
2
π
AJ
Figure 7. Mode-Recovery Timing Diagram
SCLK
CS
DIN
D0–D9
ID/QD
T/R
Rx - > Tx
ADC DIGITAL OUTPUT
SINAD SETTLES WITHIN 1dB
DAC ANALOG OUTPUT
OUTPUT SETTLES TO 10 LSB ERROR
16-BIT SERIAL DATA INPUT
t
ENABLE
,
RX
EXTERNAL T/R CONTROL
t
ENABLE
,
TX
EXTERNAL T/R CONTROL
t
WAKE, SD, ST_
TO Tx MODE OR t
ENABLE
,
TX
t
WAKE, SD, ST_
TO Rx MODE OR t
ENABLE
,
RX
T/R
Tx - > Rx
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX19706ETM 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19706ETM+ 功能描述:ADC / DAC多通道 22Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19706ETM+T 功能描述:ADC / DAC多通道 22Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19706ETM-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19706EVCMOD2 功能描述:ADC / DAC多通道 Evaluation System for the MAX19706 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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