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參數(shù)資料
| 型號(hào)： | MAX195BMDE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 85ksps ADC with 10レA Shutdown |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP16 |
| 封裝： | 0.300 INCH, SIDEBRAZED, CERAMIC, DIP-16 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 311K |
| 代理商： | MAX195BMDE |
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M
after the end of the previous conversion and
EOC
will
go high on the following CLK falling edge (Figure 4).
External Clock
The conversion clock (CLK) should have a duty cycle
between 25% and 75% at 1.7MHz (the maximum clock
frequency). For lower frequency clocks, ensure the min-
imum high and low times exceed 150ns. The minimum
clock rate for accurate conversion is 125Hz for temper-
atures up to +70°C or 1kHz at +125°C due to leakage
of the sampling capacitor array. In addition, CLK
should not remain high longer than 50ms at tempera-
tures up to +70°C or 500μs at +125°C. If CLK is held
high longer than this,
RESET
must be pulsed low to initi-
ate a recalibration because it is possible that state
information stored in internal dynamic memory may be
lost. The MAX195’s clock can be stopped indefinitely if
it is held low.
If the frequency, duty cycle, or other aspects of the
clock signal’s shape change, the offset created by cou-
pling between CLK and the analog inputs (AIN and
REF) changes. Recalibration corrects for this offset and
restores DC accuracy.
Output Data
The conversion result, clocked out MSB first, is avail-
able on DOUT only when
CS
is held low. Otherwise,
DOUT is in a high-impedance state. There are two ways
to read the data on DOUT. To read the data bits as they
are determined (at the CLK clock rate), hold
CS
low
during the conversion. To read results between conver-
sions, hold
CS
low and clock SCLK at up to 5MHz.
If you read the serial data bits as they are determined,
EOC frames the data bits (Figure 6). Conversion begins
with the first falling CLK edge, after
CONV
goes low
and the input signal has been acquired. Data bits are
shifted out of DOUT on subsequent falling CLK edges.
Clock data in on CLK’s rising edge or, if the clock
speed is greater than 1MHz, on the following falling
edge of CLK to meet the maximum CLK-to-DOUT tim-
ing specification. See the Operating Modes and
SPI/QSPI Interfaces section for additional informa-
tion. Reading the serial data during the conversion
results in the maximum conversion throughput,
because a new conversion can begin immediately after
the input acquisition period following the previous con-
version.
16-Bit, 85ksps ADC with 10μA S hutdown
8
_______________________________________________________________________________________
TRACK/HOLD
CLK
CONVERSION
BEGINS
CONVERSION
ENDS
t
AQ
*
*
THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
t
CEL
t
CW
t
CEH
t
CC2
t
CC1
EOC
CONV
Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.
SPI/QSPI are trademarks of Motorola Corp.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MAX195EVC16-DIP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Programmers, Development Systems RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX195EVKIT-DIP | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Programmers, Development Systems RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX1960EEP | 功能描述:DC/DC 開關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| MAX1960EEP+ | 功能描述:DC/DC 開關(guān)控制器 1MHz PWM Step-Down RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| MAX1960EEP+T | 功能描述:DC/DC 開關(guān)控制器 1MHz PWM Step-Down RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
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