參數(shù)資料
型號： MAX195BMDE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 16-Bit, 85ksps ADC with 10レA Shutdown
中文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP16
封裝： 0.300 INCH, SIDEBRAZED, CERAMIC, DIP-16
文件頁數(shù)： 4/28頁
文件大小： 311K
代理商： MAX195BMDE
M
16-Bit, 85ksps ADC with 10μA S hutdown
4
_______________________________________________________________________________________
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/
SHDN
= 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/
SHDN
= 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/
SHDN
= 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/
SHDN
= 0V
CONDITIONS
mW
80
Power Dissipation
μA
0.1
5
I
SSA
VSSA Shutdown Supply Current
μA
0.1
5
I
DDA
VDDA Shutdown Supply Current
μA
1.6
5
I
DDD
VDDD Shutdown Supply Current
(Note 5)
μA
0.1
5
I
SSD
VSSD Shutdown Supply Current
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
CLK
= 1.7MHz, V
REF
= +5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C.)
TIMING CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.)
Note 1:
Accuracy and dynamic performance tests performed after calibration.
Note 2:
Guaranteed by design, not tested.
Note 3:
Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable.
Note 4:
See External Clock section.
Note 5:
Measured in shutdown mode with CLK and SCLK low.
POWER REQUIREMENTS (cont.)
PARAMETER
SYMBOL CONDITIONS
T
A
= +25°C
TYP
T
A
= 0°C to
+70°C
MIN
MAX
T
A
= -40°C to
+85°C
MIN
MAX
T
A
= -55°C to
+125°C
MIN
MAX
UNITS
CONV
Pulse Width
t
CW
20
30
35
ns
CONV
to CLK Falling
Synchronization (Note 2)
t
CC1
10
10
10
ns
CONV
to CLK Rising
Synchronization (Note 2)
t
CC2
40
40
ns
Data Access Time
Bus Relinquish Time
CLK to
EOC
High
CLK to
EOC
Low
CLK to DOUT Valid
SCLK to DOUT Valid
CS
to SCLK Setup Time
CS
to SCLK Hold Time
Acquisition Time
Calibration Time
RESET
to CLK Setup Time
RESET
to CLK Hold Time
t
DV
t
DH
t
CEH
t
CEL
t
CD
t
SD
t
CSS
t
CSH
t
AQ
t
CAL
t
RCS
t
RCH
C
L
= 50pF
C
L
= 10pF
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
C
L
= 50pF
80
40
300
300
350
140
80
40
300
300
375
160
40
ns
ns
ns
ns
ns
ns
ns
ns
μs
ms
ns
ns
40
350
350
400
160
100
20
75
-10
2.4
8.2
-40
120
100
20
75
-10
2.4
8.2
-40
120
100
20
75
-10
2.4
8.2
-40
120
14,000 x t
CLK
Start-Up Time (Note 6)
t
SU
Exiting
shutdown
50
90
μs
Note 6:
Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error.
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