M
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________
23
Detailed Description
The MAX1816/MAX1994 are dual step-down controllers
for notebook computer applications. The controllers
include a CPU regulator (BUCK1) that features a
dynamically adjustable output with offset control and a
programmable suspend mode voltage. This regulator is
capable of delivering very large currents at the high
efficiencies needed for leading-edge CPU core appli-
cations. A second step-down regulator (BUCK2) is
included to generate I/O or memory supplies. Both reg-
ulators employ Maxim
’
s proprietary Quick-PWM control
architecture. A linear-regulator controller is also includ-
ed for low-voltage auxiliary power supplies. All of the
regulators have independent shutdown control inputs.
The linear regulator includes a power-good output that
is independent of the combined power-good output for
BUCK1 and BUCK2.
5V Bias Supply (V
CC
and V
DD
)
The MAX1816/MAX1994 require an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook computer
’
s 5V system supply.
Keeping the bias supply external to the IC improves effi-
ciency and eliminates the cost associated with the 5V
linear regulator that would otherwise be needed to sup-
ply the PWM controllers and gate drivers of BUCK1 and
BUCK2. If stand-alone capability is needed, the 5V sup-
ply can be generated with an external linear regulator.
The 5V bias supply must provide V
CC
for the PWM con-
troller
’
s internal reference, bias, and logic; and V
DD
for
the gate drivers. The maximum bias supply current is:
I
BIAS
= I
CC
+ f (Q
G1
+ Q
G2
+ Q
G3
+ Q
G4
)
= 20mA to 80mA (typ)
where I
CC
is 2.2mA (typ), f is the switching frequency,
and Q
G1
, Q
G2
, Q
G3
, and Q
G4
are the total gate charge
specifications at V
GS
= 5V in the MOSFET data sheets.
V+ and V
DD
can be connected if the input power source
is a fixed 4.5V to 5.5V supply. If the 5V bias supply is
powered up prior to the battery supply, the enable signals
(SKP_/
SDN
) must be delayed until the battery voltage is
present to ensure startup.
PIN
39
40
NAME
LX2
DH2
FUNCTION
BUCK2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
BUCK2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2.
BUCK2 Low-Side Gate-Driver Output. DL2 swings from PGND to V
DD
. DL2 is forced high when
MAX1816/MAX1994 detect an overvoltage fault. When the regulator powers down, DL2 is forced high if
OVP is enabled, and is forced low if OVP is disabled.
Supply Voltage Input for DL1 and DL2 Gate Drivers. Connect V
DD
to the system supply voltage (4.5V to
5.5V). Bypass V
DD
to PGND with a 2.2μF or greater ceramic capacitor.
Power Ground. Ground connection for low-side gate drivers DL1 and DL2.
BUCK1 Low-Side Gate-Driver Output. DL1 swings from PGND to V
DD
. DL1 is forced high when
MAX1816/MAX1994 detect an overvoltage fault. When the regulator powers down, DL1 is forced high.
Performance Mode Control Input. This logic-control input goes to the offset selection mux that determines
which, if any, offset control inputs are read (OFS0
–
OFS2). This input is compatible with 3.3V logic (see
Table 7).
BUCK1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1.
BUCK1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
BUCK1 Boost Flying Capacitor Connection. An optional resistor in series with BST1 allows the DH1 pullup
current to be adjusted.
41
DL2
42
V
DD
43
PGND
44
DL1
45
PERF
46
47
DH1
LX1
48
BST1
Pin Description (continued)