M
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
30
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A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V
SAG
, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where V
DROP1
and V
DROP2
are the parasitic voltage
drops in the discharge and charge paths (see
On-Time
One-Shot
), t
OFF(MIN)
is from the
Electrical Charact-
eristics
table, and K is taken from Table 3. The absolute
minimum input voltage is calculated with h = 1.
If the calculated V+
(MIN)
is greater than the required
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V
SAG
. If operation near dropout is anticipated,
calculate V
SAG
to be sure of adequate transient
response.
Dropout Design Example:
V
OUT
= 1.4V
SW
= 600kHz
K = 1.8μs; worst-case K = 1.58μs
t
OFF(MIN)
= 500ns
V
DROP1
= V
DROP2
= 100mV
Calculating again with h = 1 gives the absolute limit of
dropout:
Therefore, V
IN
must be greater than 2.2V, even with
very large output capacitance, and a practical input
voltage with reasonable output capacitance would be
2.9V.
Using Skip Mode During Suspend
For most active CPU modes, the minimum load cur-
rents are too high to benefit from pulse-skipping opera-
tion, so PWM mode should be used exclusively. Skip
mode can, in fact, be a hindrance to properly executing
output voltage transitions (see
Forced PWM Mode
).
However, processor suspend currents can be low
enough to benefit from low-power pulse skipping.
For processors with three-state outputs, SKP/
SDN
and
SUS may be directly controlled. If only digital logic is
available, SKP/
SDN
and SUS may be controlled with
two digital outputs with the circuit shown in Figure 11.
In normal operation, SKP/
SDN
remains biased at 2V by
the resistive voltage-divider and the MAX1813
’
s internal
circuitry. When the circuit goes into suspend mode
(SUS high), the pin remains biased at 2V for approxi-
mately 200μs before it goes high. This delay causes the
MAX1813 to remain in PWM mode long enough to
correctly complete the negative output voltage transi-
tion to the suspend-state voltage. Thereafter, the
MAX1813 will operate with low-quiescent-current SKIP
mode. When the circuit returns to normal operation
(SUS low), the delay on the SKP/
SDN
does not affect
the transition dynamics because the MAX1813 auto-
matically returns to PWM mode and continues to supply
current until the output is in regulation. The ON/
OFF
signal overrides both normal forced-PWM operation
and suspend mode.
Using the ZMODE Multiplexer
There are many ways to use the versatile ZMODE multi-
plexer. The preferred method will depend on when and
how the VID DAC codes for the various states are
determined. If the output voltage codes are fixed at PC
board design time, program both codes with a simple
combination of pin-strap connections and series resis-
tors (Figure 12). If the output voltage codes are chosen
during PC board assembly, both codes can be inde-
pendently programmed with resistors (Figure 13). This
matrix of 10 resistor-footprints can be programmed to
all possible logic-mode and impedance-mode code
combinations with only 5 resistors.
Often, the CPU pins provide one set of codes that are
typically used with pullup resistors to provide the logic
mode VID code, and resistors in series with D0
–
D4 set
the impedance-mode code. Since some of the CPU
’
s
VID pins may float, the open-circuit pins can present a
problem for the ZMODE multiplexer
’
s impedance
mode. For impedance mode to work, any pins intended
to be low during this mode must appear to be low
impedance at least for the 4μs sampling interval.
V
IN MIN
(
)
.
=
+
=
1.4V+100mV
1-(0.5 s 1.0/1.58 s)
100mV 100mV
2 V
V
IN MIN
(
)
.
=
+
=
1.4V+100mV
1-(0.5 s 1.5/1.58 s)
100mV 100mV
2 V
9
V
IN MIN
(
)
=
V
+V
1-
h t
K
V
V
OUT
DROP1
OFF(MIN)
DROP2
DROP1
+