M
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
______________________________________________________________________________________
29
V
P-P1
= 2 x (ESR
COUT
x
I
LOAD
) + V
SAG
+ V
SOAR
where V
SAG
and V
SOAR
are defined in Figure 10.
Setting the converter to regulate at a lower voltage
when under load allows a larger voltage step when the
output current suddenly decreases (Figure 9). So the
total voltage change for a voltage-positioned circuit is:
V
P-P2
= (ESR
COUT
x
LOAD
) + V
SAG
+ V
SOAR
where V
SAG
and V
SOAR
are defined in the
Design
Procedure
. Since the amplitudes are the same for both
circuits (V
P-P1
= V
P-P2
), the voltage-positioned circuit
requires only twice the ESR. Since the ESR specifica-
tion is achieved by paralleling several capacitors, fewer
units are needed for the voltage-positioned circuit.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in
R
SENSE
. However, the gain of the voltage positioning
block reduces the power dissipation in R
SENSE
. For a
nominal 1.4V, 22A output (R
LOAD
= 63.6m
), reducing
the output voltage 6% gives a 1.32V output voltage and
a 20.7A output current. Given these values, CPU power
consumption is reduced from 30.8W to 27.3W. The
additional power consumption of R
SENSE
is:
2.0m
x (20.7A)
2
= 0.86W
and the overall power savings is:
30.8W - (27.3W + 0.86W) = 2.62W
In effect, 2.62W of CPU dissipation is saved and the
power supply dissipates much of the savings, but both
the net savings and the transfer of dissipation away
from the hot CPU are beneficial. Effective efficiency is
defined as the efficiency required of a non-voltage-
positioned circuit to equal the total dissipation of a volt-
age-positioned circuit for a given CPU operating
condition.
Calculate effective efficiency:
1) Start with the efficiency data for the positioned circuit
V
IN
, I
IN
, V
OUT
, I
OUT
).
2) Model the load resistance for each data point:
R
LOAD
= V
OUT
/ I
OUT
3) Calculate the output current that would exist for each
R
LOAD
data point in a nonpositioned application:
I
NP
= V
NP
/ R
LOAD
where V
NP
= 1.4V (in this example).
4) Calculate effective efficiency as:
Effective efficiency = (V
NP
x I
NP
) / (V
IN
x I
IN
) = calcu-
lated nonpositioned power output divided by the
measured voltage-positioned power input.
5) Plot the efficiency data point at the nonpositioned
current, I
NP
.
The effective efficiency of voltage-positioned circuits is
shown in the
Typical Operating Characteristics
.
Dropout Performance
The output-voltage adjustable range for continuous-
conduction operation is restricted by the nonadjustable
500ns (max) minimum off-time one-shot. For best
dropout performance, use the slower (200kHz) on-time
settings. When working with low input voltages, the
duty-factor limit must be calculated using worst-case
values for on- and off-times. Manufacturing tolerances
and internal propagation delays introduce an error to
the TON K-factor. This error is greater at higher fre-
quencies (Table 3). Also, keep in mind that transient-
response performance of buck regulators operated
close to dropout is poor, and bulk output capacitance
must often be added (see the V
SAG
equation in the
Design Procedure
).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (
I
DOWN
)
as much as it ramps up during the on-time (
I
UP
). The
ratio h =
I
UP
/
I
DOWN
is an indicator of ability to slew
the inductor current higher in response to increased
load and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current cannot increase as much during each
switching cycle, and V
SAG
greatly increases unless
additional output capacitance is used.
I
LOAD
CAPACITOR SOAR
(ENERGY IN L
TRANSFERRED TO C
OUT
)
CAPACITIVE SAG
(dV/dt = I
OUT
/C
OUT
)
RECOVERY
ESR STEP-DOWN
AND STEP-UP
(I
STEP x
ESR)
V
OUT
Figure 10. Transient-Response Regions