M
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
______________________________________________________________________________________
19
put voltage in 25mV increments at the clock rate set by
R
TIME
until the MAX1813 reaches the selected output
voltage. The MAX1813 does not feature traditional vari-
able current-limit soft-start, so full output current is
immediately available. Once the slew-rate controller ter-
minates, output undervoltage fault blanking period
ends, and the output voltage is in regulation, PGOOD
goes high.
Leave SKP/
SDN
floating for forced-PWM operation, or
connect SKP/
SDN
to V
CC
for normal operation. During
all transitions, the MAX1813 uses PWM mode while the
slew-rate controller is active. Exiting shutdown clears
the fault latch.
Current-Limit Circuit (ILIM)
The current-limit circuit employs a unique
“
valley
”
cur-
rent-sensing algorithm. If the current-sense signal is
above the current-limit threshold, the MAX1813 will not
initiate a new cycle (Figure 4). The actual peak current
is greater than the current-limit threshold by an amount
equal to the inductor ripple current. Therefore the exact
current-limit characteristic and maximum load capabili-
ty are a function of the current-limit threshold, inductor
value, and input voltage. The reward for this uncertainty
is robust, loss-less over-current sensing. When com-
bined with the undervoltage protection circuit, this cur-
rent-limit method is effective in almost every
circumstance.
There is also a negative current limit that prevents
excessive reverse inductor currents when V
OUT
is sink-
ing current. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
therefore tracks the positive current limit when ILIM is
adjusted.
The MAX1813 measures the current by sensing the
voltage between VPCS and PGND. Connect an external
sense resistor between the source of the low-side N-
channel MOSFET and PGND. The signal provided by
this current-sense resistor is also used for voltage posi-
tioning (see
Setting Voltage Positioning
). Reducing the
sense voltage increases the relative measurement
error. However, the configuration eliminates the uncer-
tainty of using the low-side MOSFET on-resistance to
measure the current, so the resulting current-limit toler-
ance is tighter when sensing with a 1% sense resistor.
The voltage at ILIM sets the current-limit threshold. For
voltages from 500mV to 2V, the current-limit threshold
voltage is precisely 0.1 x V
ILIM
. Set this voltage with a
resistive divider between REF and GND. The current-
limit threshold defaults to 50mV when ILIM is tied to
V
CC
. The logic threshold for switchover to this 50mV
default value is approximately V
CC
- 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don
’
t corrupt the cur-
rent-sense signals seen by VPCS and GND. The IC
must be mounted close to the current-sense resistor
with short, direct traces making a Kelvin sense connec-
tion (see
PC Board Layout Guidelines
).
MOSFET Gate Drivers (DH and DL)
The DH and DL drivers are optimized for driving mod-
erate-sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
V
IN
- V
OUT
differential exists. An adaptive dead-time
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time
circuit to work properly. Otherwise, the sense circuitry
in the MAX1813 will interpret the MOSFET gate as
“
off
”
while there is actually charge still left on the gate. Use
very short, wide traces (50 to 100 mils wide if the MOS-
FET is 1 inch from the device). The dead time at the
other edge (DH turning off) is determined by a fixed
35ns internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.4
(typ) on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time
of the LX node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, some
combinations of high- and low-side FETs may cause
excessive gate-drain coupling, leading to poor
I
I
LIMIT
I
LOAD
0
TIME
I
PEAK
Figure 4.
“
Valley
”
Current-Limit Threshold Point