參數(shù)資料
型號: MAX1718EEI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-II
中文描述: SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28
封裝: 0.150 INCH, 0.025 INCH PITCH, MO-137AD, QSOP-28
文件頁數(shù): 21/35頁
文件大?。?/td> 700K
代理商: MAX1718EEI
M
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
______________________________________________________________________________________
21
interval of 2
R
PULLUP
4.7nF is recommended
between ZMODE samples.
In some cases, it is desirable to determine the
Impedance mode code during system boot so that sev-
eral processor types can be used without hardware
modifications. Figure 14 shows one way to implement
this function. The desired code is determined by the
system BIOS and programmed into one register of the
MAX1609 using the SMBus
serial interface. The
MAX1609
s other register is left in its power-up state (all
outputs high impedance). When
SMBSUS
is low, the
outputs are high impedance and do not affect the
Logic-mode VID code setting. When
SMBSUS
is high,
the programmed register is selected, and the MAX1609
forces a low impedance on the appropriate VID input
pins. The ZMODE signal is delayed relative to the
SMB-
SUS
pin because the VID pins that are pulled low by
the MAX1609 take significant time to rise when they are
released. One additional benefit of using the MAX1609
for this application is that the application uses only five of
the MAX1609
s high-voltage, open-drain outputs. The
other three outputs can be used for other purposes.
Output Voltage Transition Timing
The MAX1718 is designed to perform output voltage
transitions in a controlled manner, automatically mini-
mizing input surge currents. This feature allows the cir-
cuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output volt-
age level with the lowest possible peak currents for a
given output capacitance. This makes the IC ideal for
IMVP-IICPUs.
IMVP-II CPUs operate at two distinct clock frequencies
and require three distinct VID settings. When transition-
ing from one clock frequency to the other, the CPU first
goes into a low-power state, then the output voltage
and clock frequency are changed. The change must
be accomplished in 100μs or the system may halt.
MAX1718
D4
D3
D2
D1
D0
ZMODE
ZMODE = HIGH = 1.25V
ZMODE = LOW = 1.15V
1k
1k
100k
1k
100k
2.7V TO 5.5V
NOTE:
USE PULLUP FOR LOGIC MODE 1, PULLDOWN FOR LOGIC MODE 0.
USE
100k
FOR IMPEDANCE MODE 1,
1k
FOR IMPEDANCE MODE 0.
Figure 12. Using the Internal Mux with Both VID Codes Resistor Programmed
ZMODE
SUS
OUTPUT VOLTAGE
DETERMINED BY:
GND
V
CC
X
GND
GND
V
CC
Logic Level of D0
D4
Impedance of D0
D4
Logic Levels of S0, S1
Table 5. DAC Mux Operation
SMBus is a trademark of Intel Corp.
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