參數(shù)資料
型號(hào)： MAX1711
廠商： Maxim Integrated Products, Inc.
英文描述： High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs
中文描述： 高速、數(shù)字可調(diào)、降壓型控制器，用于筆記本電腦
文件頁(yè)數(shù)： 21/28頁(yè)
文件大?。?/td> 299K
代理商： MAX1711
propagation delays introduce an error to the TON K-fac-
tor. This error is higher at higher frequencies (Table 5).
Also, keep in mind that transient response performance
of buck regulators operated close to dropout is poor,
and bulk output capacitance must often be added (see
V
SAG
equation in the Design Procedure).
Dropout Design Example: V
BATT
= 3V min, V
OUT
=
2V, f = 300kHz.
The required duty is (V
OUT
+ V
SW
) /
(V
BATT
- V
SW
) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The
worst-case on-time is (V
OUT
+ 0.075) / V
BATT
·
K =
2.075V / 3V
·
3.35μs-V
·
90% = 2.08μs. The IC duty-fac-
tor limitation is:
which meets the required duty.
Remember to include inductor resistance and MOSFET
on-state voltage drops (V
SW
) when doing worst-case
dropout duty-factor calculations.
All-Ceramic-Capacitor Application
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR, are non-combustible,
are relatively small, and are nonpolarized. On the other
hand, they’re expensive and brittle, and their ultra-low
ESR characteristic can result in excessively high ESR
zero frequencies (affecting stability). In addition, they
can cause output overshoot when going abruptly from
full-load to no-load conditions, unless there are some
bulk tantalum or electrolytic capacitors in parallel to
absorb the stored energy in the induc-
tor. In some cases, there may be no room for electrolyt-
ics, creating a need for a DC-DC design that uses noth-
ing but ceramics.
The all-ceramic-capacitor application of Figure 7 has the
same basic performance as the 7A Standard Application
Circuit, but replaces the tantalum output capacitors with
ceramics. This design relies on having a minimum of
5m
parasitic PC board trace resistance in series with
the capacitor in order to reduce the ESR zero frequency.
This small amount of resistance is easily obtained by
locating the MAX1710/MAX1711 circuit two or three inch-
es away from the CPU, and placing all the ceramic
capacitors close to the CPU. Resistance values higher
than 5m
just improve the stability (which can be
observed by examining the load-transient response
characteristic as shown in the Typical Operating
Characteristics). Avoid adding excess PC board trace
resistance, as there’s an efficiency penalty. 5m
is suffi-
cient for the 7A circuit.
Output overshoot determines the minimum output
capacitance requirement. In this example, the switching
frequency has been increased to 550kHz and the induc-
tor value has been reduced to 0.5μH (compared to
300kHz and 2μH for the standard 7A circuit) in order to
minimize the energy transferred from inductor to capaci-
tor during load-step recovery. Even so, the amount of
overshoot is high enough (80mV) that for the MAX1710,
it’s wise to disable OVP or use the MAX1711 with its fixed
2.25V overvoltage protection threshold to avoid tripping
the fault latch (see the overshoot equation in the Output
Capacitor Selection section). The efficiency penalty for
operating at 550kHz is about 2% to 3%, depending on
the input voltage.
Two optional 1k
resistors are placed in series with FB
and FBS. These resistors prevent the negative output
voltage spike (that results from tripping OVP) from
pulling
SHDN
low via its internal ESD diode, which tends
to clear the fault latch, causing “hiccup” restarts.
Setting V
OUT
with a Resistor-Divider
The output voltage can be adjusted with a resistor-
divider rather than the DAC if desired (Figure 8). The
drawback of this practice is that the on-time doesn’t
automatically receive correct compensation for changing
output voltage levels. This can result in variable switch-
ing frequency as the resistor ratio is changed and/or
excessive switching frequency. The equation for adjust-
ing the output voltage is:
V
V
R
R
OUT
FB
=
(
)
+
1
1
1
2
%
DUTY
t
t
t
s
ns
ON MIN
+
)
ON MIN
(
OFF MAX
(
=
=
μ +
=
(
)
)
.
2 08
500
80. %
M
High-S peed, Digitally Adjusted
S tep-Down Controllers for Notebook CPUs
______________________________________________________________________________________
21
DL
DH
FB
FBS
GNDS
V
BATT
V
OUT
R1
1k
R2
MAX1710
Figure 8. Setting V
OUT
with a Resistor-Divider
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