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MAX16047A/MAX16049A
Detailed Description
Getting Started
The MAX16047A is capable of managing up to twelve
system voltages simultaneously, and the MAX16049A
can manage up to eight system voltages. After boot-
up, if EN is high and the Software Enable bit is set to
‘0,’ an internal multiplexer cycles through each input. At
each multiplexer stop, the 10-bit ADC converts the
monitored analog voltage to a digital result and stores
the result in a register. Each time the multiplexer finish-
es a conversion (12.45s max), internal logic circuitry
compares the conversion results to the overvoltage and
undervoltage thresholds stored in memory. If a conver-
sion violates a programmed threshold, the conversion
can be configured to generate a fault. Logic outputs
can be programmed to depend on many combinations
of faults. Additionally, faults are programmable to trig-
ger the nonvolatile fault logger, which writes all fault
information automatically to the EEPROM and write-pro-
tects the data to prevent accidental erasure.
The MAX16047A/MAX16049A contain both I2C/SMBus-
compatible and JTAG serial interfaces for accessing reg-
isters and EEPROM. Use only one interface at any given
time. For more information on how to access the internal
memory through these interfaces, see the
I2C/SMBus-
Compatible Serial Interface and JTAG Serial Interface
sections. Registers are divided into three pages with
access controlled by special I2C and JTAG commands.
The factory-default values at POR (power-on reset) for
all RAM registers are ‘0’s. POR occurs when VCC reach-
es the undervoltage-lockout threshold (UVLO) of 2.85V
(max). At POR, the device begins a boot-up sequence.
During the boot-up sequence, all monitored inputs are
masked from initiating faults and EEPROM contents are
copied to the respective register locations. During boot-
up, the MAX16047A/MAX16049A are not accessible
through the serial interface. The boot-up sequence can
take up to 1.5ms, after which the device is ready for
normal operation. RESET is low during boot-up and
asserts after boot-up for its programmed timeout period
once all monitored channels are within their respective
thresholds. During boot-up, the GPIOs and EN_OUTs
are high impedance.
Accessing the EEPROM
The MAX16047A/MAX16049A memory is divided into
three separate pages. The default page, selected by
default at POR, contains configuration bits for all func-
tions of the part. The extended page contains the ADC
conversion results and GPIO input and output regis-
ters. Finally, the EEPROM page contains all stored con-
figuration information as well as saved fault data and
user-defined data. See the
Register Map table for more
information on the function of each register.
During the boot-up sequence, the contents of the
EEPROM (r0Fh to r7Dh) are copied into the default
page (r0Fh to r7Dh). Registers r00h to r0Eh of the EEP-
ROM page contain saved fault data.
The JTAG and I2C interfaces provide access to all
three pages. Each interface provides commands to
select and deselect a particular page:
98h(I2C)/09h(JTAG)—Switches to the extended
page. Switch back to the default page with
99h(I2C)/0Ah(JTAG).
9Ah(I2C)/0Bh(JTAG)—Switches to the EEPROM
page. Switch back to the default page with
9Bh(I2C)/0Ch(JTAG).
See the
I2C/SMBus-Compatible Serial Interface or the
JTAG Serial Interface section.
Power
Apply 3V to 14V to VCC to power the MAX16047A/
MAX16049A. Bypass VCC to ground with a 10F capaci-
tor. Two internal voltage regulators, ABP and DBP, supply
power to the analog and digital circuitry within the device.
Do not use ABP or DBP to power external circuitry.
ABP is a 2.85V (typ) voltage regulator that powers the
internal analog circuitry. Bypass the ABP output to GND
with a 1F ceramic capacitor installed as close to the
device as possible.
DBP is an internal 2.7V (typ) voltage regulator. EEPROM
and digital circuitry are powered by DBP. All push-pull
outputs are referenced to DBP. DBP supplies the input
voltage to the internal charge pumps when the program-
mable outputs are configured as charge-pump outputs.
Bypass the DBP output to GND with a 1F ceramic
capacitor installed as close as possible to the device.
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
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