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參數(shù)資料
| 型號： | MAX14824GTG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC IO-LINK MASTER TXRX 24TQFN |
| 標準包裝： | 2,500 |
| 系列： | * |
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MAX14824
IO-Link Master Transceiver
Mode Register [R1, R0] = [1,1]
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
RST
WuEnBit
X
C/QFault
UV24
OTemp
UV33En
LDO33Dis
Read/Write
R/W
R
R/W
POR State
0
X = Unused bits.
Use the Mode register to reset the device and manage the 3.3V LDO. The Mode register has bits that represent the current
status of fault conditions. When writing to the Mode register, the contents of the fault indication bits (bits 2 to 4) do not change.
BIT
NAME
DESCRIPTION
D7
RST
Register Reset. Set RST to 1 to reset all registers to their default power-up state. Then
set RST to 0 for normal operation.
The Status register is cleared and IRQ deasserts (if asserted) when RST = 1. Interrupts
are not generated while RST = 1.
D6
WuEnBit
Auto Wake-Up Polarity Enable. Drive the WUEN input high or set the WuEnBit bit to 1
to enable wake-up generation. When auto wake-up polarity is enabled, the device sam-
ples the logic state of C/Q and uses this as the basis for determining the subsequent
wake-up pulse that is initiated through a high-to-low pulse on the TXQ and TXC inputs.
Set the WuEnBit to 1 before a negative-going, 80s (typ) wake-up pulse is transmitted to
ensure that the device produces the correct polarity wake-up pulse on the C/Q output.
For example, if C/Q is connected to a voltage high, then it pulls the line low for the wake-
up pulse duration. If C/Q is connected to a voltage low, then it pulls the line high for the
wake-up pulse duration. Clear WuEnBit after the wake-up has been generated (Table 6).
D5
X
Unused
D4
C/QFault
C/Q Fault Status. The C/QFault bit is set when a short circuit or voltage fault occurs at
the C/Q driver output (see the C/Q Fault Detection section for more information). The
C/QFault and C/QFaultInt bits are both set when a fault occurs on C/Q. C/QFault is
cleared when the fault is removed.
D3
UV24
VCC Undervoltage Condition. Both the UV24 and the UV24Int bits are set when VCC
falls below VCCUVLO. UV24 is cleared when VCC rises above the VCC threshold. V5
must be present for VCC undervoltage monitoring.
D2
OTemp
Temperature Warning. The OTemp bit is set when a high-temperature condition
occurs on the device. Both the OTempInt interrupt in the Status register and the OTemp
bit are set when the junction temperature of the die rises to above +115NC (typ). The
OTemp bit is cleared when the junction temperature falls below +95NC (typ).
D1
UV33En
LDO33 UV Enable. Set the UV33En bit to 1 to assert the UV output when LDO33 volt-
age falls below the 2.4V (typ) undervoltage lockout threshold. The UV33En bit does
not affect the UV33Int bit in the Status register; IRQ asserts when VLDO33 falls below
VLDO33UVLO regardless of the state of UV33En.
D0
LDO33Dis
LDO33 Enable/Disable. Set LDO33Dis to 1 to disable the 3.3V linear regulator (LDO33).
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