參數(shù)資料
型號： MAX14824GTG+T
廠商： Maxim Integrated Products
文件頁數(shù)： 10/28頁
文件大?。?/td> 0K
描述： IC IO-LINK MASTER TXRX 24TQFN
標(biāo)準(zhǔn)包裝： 2,500
系列： *
18
MAX14824
IO-Link Master Transceiver
Register Functionality
The device has four 8-bit-wide registers for configuration and monitoring (Table 1). R1 and R0 are the register address.
Table 1. Register Summary
R1/R0 = Register address, X = Unused bits.
Status Register [R1, R0] = [0,0]
REGISTER
R1
R0
D7
D6
D5
D4
D3
D2
D1
D0
Status
0
X
DiLvl
QLvl
C/QFaultInt
UV33Int
UV24Int
OTempInt
CQConfig
0
1
RxFilter
HiSlew
C/Q_N/P
C/Q_PP
C/QDEn
Q
RxDis
C/QLoad
DIOConfig
1
0
X
LiDis
DiLoad
Mode
1
RST
WuEnBit
X
C/QFault
UV24
OTemp
UV33En
LDO33Dis
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
X
DiLvl
QLvl
C/QFaultInt
UV33Int
UV24Int
OTempInt
Read/Write
R
POR State
0
U
0
Reset Upon Read
Yes
No
Yes
X = Unused bits.
U = Unknown. These bits are dependent on the DI logic and C/Q inputs.
The Status register reflects the logic levels of C/Q and DI and shows the source of interrupts that cause an IRQ hardware
interrupt. The IRQ interrupt is asserted when an alarm condition (OTemp, UV33En, UV24, C/QFault) is detected. All bits in
the Status register are read-only. The interrupt bits return to the default state after the Status register is read. If a C/Q fault
condition persists, the C/QFaultInt bit is immediately set after the Status register is read.
BIT
NAME
DESCRIPTION
D7:D6
X
Unused
D5
DiLvl
DI Logic Level. The DiLvl bit mirrors the current logic level at the DI input. It is the
inverse of the LI output and is always active regardless of the state of the LiDis bit
(Table 2). DiLvl does not affect IRQ. DiLvl is not changed when the Status register is
read.
D4
QLvl
C/Q Logic Level. The QLvl bit is the inverse of the logic level at C/Q. QLvl is 1 when the
C/Q input level is low (< 8V) and is 0 when the C/Q logic level is high (> 13V) (Table 3).
QLvl remains active when the C/Q receiver is disabled (RxDis = 1). QLvl does not affect
IRQ. QLvl is not changed when the Status register is read.
D3
C/QFaultInt
C/Q Fault Interrupt. The C/QFaultInt interrupt bit and C/QFault bit (in the Mode register)
are set when a short circuit or voltage fault occurs on the C/Q driver output (see the C/Q
Fault Detection section for more information). IRQ asserts when C/QFault is 1. Read the
Status register to clear the C/QFaultInt bit and deassert IRQ.
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