VDI
參數(shù)資料
型號： MAX14824GTG+T
廠商： Maxim Integrated Products
文件頁數(shù)： 11/28頁
文件大小： 0K
描述： IC IO-LINK MASTER TXRX 24TQFN
標(biāo)準(zhǔn)包裝： 2,500
系列： *
19
MAX14824
IO-Link Master Transceiver
Table 2. DiLvl and LI Output
Table 3. QLvl and RX Output
VDI (V)
DiLvl BIT
LI OUTPUT
< 5.2
0
High
> 8
1
Low
VC/Q (V)
QLvl BIT
RX OUTPUT
< 8
1
High
>13
0
Low
BIT
NAME
DESCRIPTION
D2
UV33Int
Internal 3.3V LDO (LDO33) Undervoltage Warning. Both the UV33Int interrupt bit and
the UV33En bit (in the Mode register) are set when VLDO33 falls below the 2.4V LDO33
undervoltage threshold. If UV33En is set in the Mode register, IRQ asserts low when the
UV33Int bit is 1. Read the Status register to clear the UV33Int bit and deassert IRQ.
Set the UV33En bit to 1 in the Mode register to enable undervoltage monitoring for
UV33Int. When enabled, UV asserts high when the UV33Int bit is 1. UV deasserts when
VLDO33 rises above the LDO33 undervoltage threshold.
D1
UV24Int
VCC Undervoltage Interrupt. The UV24Int interrupt bit and the UV24 bit (in the Mode
register) are set when the VCC voltage falls below the 7.4V undervoltage threshold. IRQ
asserts low when the UV24Int bit is 1. Read the Status register to clear the UV24Int bit
and deassert IRQ. VCC undervoltage detection cannot be disabled.
D0
OTempInt
Overtemperature Warning. The OTempInt interrupt bit and the OTemp bit (in the Mode
register) are set when a high-temperature condition is detected by the device. OTemp
is set when the temperature of the die exceeds +115NC (typ). OTempInt is set and IRQ
asserts when the OTemp bit is 1. The OTempInt bit is cleared and IRQ deasserts when
the Status register is read.
Once cleared, OTempInt is not reset if the die temperature remains above the thermal
warning threshold and does not fall below +95
°C.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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