參數(shù)資料
型號： MAX1419ETN
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
中文描述： 1-CH 15-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56
封裝： 8 X 8 MM, 0.80 MM HEIGHT, MO-220WLLD-5, TQFN-56
文件頁數(shù)： 4/18頁
文件大?。?/td> 219K
代理商： MAX1419ETN
M
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applic ations
4
_______________________________________________________________________________________
Note 1:
Dynamic performance is based on a 32,768-point data record with a sampling frequency of f
SAMPLE
= 100.007936MHz, an
input frequency of f
IN
= f
SAMPLE
x (4915/32768) = 15.000580MHz, and a frequency bin size of 3052Hz. Close-in (f
IN
±
36.6kHz) and low-frequency (DC to 73.2kHz) bins are excluded from the spectrum analysis.
Note 2:
Apply the same voltage levels to DV
CC
and DRV
CC
.
Note 3:
Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥
+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 3.3V)
CLKP/CLKN Duty Cycle
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Duty Cycle
t
AD
t
DAT
t
DAV
50
±
5
230
4.1
6.3
%
ps
ns
ns
(Note 3)
(Note 3)
2.8
5.3
6.5
8.6
Pipeline Latency
t
LATENCY
3
Clock
cycles
CLKP Rising Edge to DATA Not
Valid
t
DNV
(Note 3)
2.5
3.4
5.2
ns
CLKP Rising Edge to DATA Valid
(guaranteed)
t
DGV
(Note 3)
3.2
4.4
7.4
ns
DATA Setup Time (Before DAV
Rising Edge)
t
SETUP
(Note 3)
t
CLKP
+
0.2
t
CLKP
+
1.7
t
CLKP
+
2.8
ns
DATA Hold Time (After DAV
Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.5
t
CLKN
-
2.7
t
CLKN
-
2.0
ns
POWER REQUIREMENTS
Analog Supply Voltage Range
AV
CC
5
±3%
V
Digital-Supply Voltage Range
DV
CC
(Note 2)
2.3 to
2.5
V
Output-Supply Voltage Range
DRV
CC
(Note 2)
2.3 to
2.5
V
Analog Supply Current
I
AVCC
390
440
mA
Digital + Output Supply Current
I
DVCC
+
I
DRVCC
PDISS
f
CLK
= 100MHz, C
L
= 5pF
38
44
mA
Total Power Dissipation
2045
mW
相關PDF資料
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MAX1429 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications
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