參數(shù)資料
型號(hào)： MAX1419ETN
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
中文描述： 1-CH 15-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56
封裝： 8 X 8 MM, 0.80 MM HEIGHT, MO-220WLLD-5, TQFN-56
文件頁(yè)數(shù)： 3/18頁(yè)
文件大?。?/td> 219K
代理商： MAX1419ETN
M
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applic ations
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥
+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
75.3
75.1
74.8
75.0
74.9
71.1
90.0
90.0
74.0
96.0
94.0
92.0
MAX
UNITS
f
IN
= 5MHz at -1dBFS
f
IN
= 15MHz at -1dBFS
f
IN
= 35MHz at -1dBFS
f
IN
= 5MHz at -1dBFS
f
IN
= 15MHz at -1dBFS
f
IN
= 35MHz at -1dBFS
f
IN
= 5MHz at -1dBFS
f
IN
= 15MHz at -1dBFS
f
IN
= 35MHz at -1dBFS
f
IN
= 5MHz at -1dBFS
f
IN
= 15MHz at -1dBFS
f
IN
= 35MHz at -1dBFS
f
IN1
= 10MHz at -7dBFS,
f
IN2
= 15MHz at -7dBFS
72.1
Signal-to-Noise
Ratio (Note 1)
SNR
dB
71.7
Signal-to-Noise
and Distortion
(Note 1)
SINAD
dB
84.0
Spurious-Free Dynamic Range
(HD2 and HD3)
(Note 1)
SFDR1
dBc
85.0
Spurious-Free Dynamic Range
(HD4 and Higher)
(Note 1)
SFDR2
dBc
Two-Tone Intermodulation
Distortion
TTIMD
-85
dBc
Two-Tone Spurious-Free
Dynamic Range
SFDR
TT
f
I N 1
= 10M H z at - 10d BFS < f
I N 1
< - 100d BFS
f
IN 2
= 15M H z at - 10d BFS < f
IN 2
< - 100d BFS
-100
dBFS
DIGITAL OUTPUTS (D0–D14, DAV, DOR)
Digital Output-Voltage Low
V
OL
0.5
V
Digital Output-Voltage High
V
OH
DRV
CC
- 0.5
V
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 2.5V)
CLKP/CLKN Duty Cycle
Duty Cycle
50
±
5
%
Effective Aperture Delay
Output Data Delay
Data Valid Delay
t
AD
t
DAT
t
DAV
230
4.5
6.5
ps
ns
ns
(Note 3)
(Note 3)
3.0
5.3
7.5
8.7
Pipeline Latency
t
LATENCY
(Note 3)
3
Clock
cycles
CLKP Rising Edge to DATA Not
Valid
t
DNV
(Note 3)
2.6
3.8
5.7
ns
CLKP Rising Edge to DATA Valid
(guaranteed)
t
DGV
(Note 3)
3.4
5.2
8.6
ns
DATA Setup Time (Before DAV
Rising Edge)
t
SETUP
(Note 3)
t
CLKP
- 0.5
t
CLKP
+ 1.3
t
CLKP
+
2.4
ns
DATA Hold Time (After DAV
Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.6
t
CLKN
-
2.8
t
CLKN
-
2.0
ns
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