參數(shù)資料
型號: MAX1407CAI+
廠商: Maxim Integrated Products
文件頁數(shù): 41/48頁
文件大?。?/td> 0K
描述: IC DAS 16BIT LP 28-SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 46
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 16 b
采樣率(每秒): 60
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 2.7 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 28-SSOP
包裝: 管件
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
46
______________________________________________________________________________________
the placement of the crystal on the PC board layout to
insure that extra clock “ticks” do not couple onto the
crystal pins.
1) It is important to place the crystal as close as possi-
ble to the CLKIN and CLKOUT pins. Keeping the
trace lengths between the crystal and pins as small
as possible reduces the probability of noise cou-
pling by reducing the length of the “antennae”.
Keeping the trace lengths small also decreases the
amount of stray capacitance.
2) Keep the crystal bond pads and trace width to the
CLKIN and CLKOUT pins as small as possible. The
larger these bond pads and traces are, the more
likely it is that noise can couple from adjacent signals.
3) If possible, place a guard ring (connect to ground)
around the crystal. This helps to isolate the crystal
from noise coupled from adjacent signals.
4) Insure that no signals on other PC board layers run
directly below the crystal or below the traces to the
CLKIN and CLKOUT pins. The more the crystal is
isolated from other signals on the board, the less
likely it is that noise will be coupled into the crystal.
There should be a minimum of 0.200 inches
between any digital signal and any trace connected
to CLKIN or CLKOUT.
5) It may also be helpful to place a local ground plane
on the PC board layer immediately below the crystal
guard ring. This helps to isolate the crystal from
noise coupling from signals on other PC board lay-
ers. Note: The ground plane needs to be in the
vicinity of the crystal only and not on the entire
board.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function (with offset and gain error
removed) from a straight line. This straight line can be
either a best straight-line fit or a line drawn between the
endpoints of the transfer function, once offset and gain
errors have been nullified. The static linearity parame-
ters for the MAX1407/MAX1408/MAX1409/MAX1414 are
measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
TOP VIEW
CS
WU2
RESET
WU1
INT
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
DVDD
DGND
SCLK
REF
IN0
OUT1
FB1
DIN
DOUT
CLKIN
CPLL
AVDD
AGND
12
11
9
10
CLKOUT
FOUT
MAX1409
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN5
IN3
DVDD
DGND
SCLK
DIN
DOUT
CLKIN
CLKOUT
FOUT
IN2
IN1
CPLL
AVDD
AGND
REF
IN0
IN4
IN6
DO
IN7
MAX1408
CS
WU2
RESET
WU1
INT
DRDY
SHDN
Pin Configurations (continued)
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