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參數(shù)資料
| 型號： | MAX1364MEUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYSTEM MON 12BIT 4CH 10-UMAX |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 133k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 444.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF =
0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Hold Time for START (S)
Condition
tHD, STA
0.6
s
Low Period of the SCL Clock
tLOW
1.3
s
High Period of the SCL Clock
tHIGH
0.6
s
Setup Time for a Repeated
START Condition (Sr)
tSU, STA
0.6
s
Data Hold Time
tHD, DAT
0
900
ns
Data Setup Time
tSU, DAT
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
Measured from 0.3VDD to 0.7VDD
0
300
ns
Fall Time of SDA Transmitting
tF
Measured from 0.3VDD to 0.7VDD
0
300
ns
Setup Time for STOP (P)
Condition
tSU, STO
0.6
s
Capacitive Load for Each Bus
Line
CB
400
pF
Pulse Width of Spike Suppressed
50
ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Figures 1a, 2) (Note 12)
Serial Clock Frequency
fSCLH
(Note 13)
1.7
MHz
Hold Time, Repeated START
Condition (Sr)
tHD, STA
160
ns
Low Period of the SCL Clock
tLOW
(Note 13)
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a Repeated
START Condition (Sr)
tSU, STA
160
ns
Data Hold Time
tHD, DAT
(Note 14)
0
150
ns
Data Setup Time
tSU, DAT
10
ns
Rise Time of SCL Signal, Current
Source Enabled
tRCL
Measured from 0.3VDD to 0.7VDD
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
Measured from 0.3VDD to 0.7VDD
20
160
ns
Fall Time of SCL Signal
tFCL
Measured from 0.3VDD to 0.7VDD
20
80
ns
Rise Time of SDA Signal
tRDA
Measured from 0.3VDD to 0.7VDD
20
160
ns
Fall Time of SDA Signal
tFDA
Measured from 0.3VDD to 0.7VDD
20
160
ns
Setup Time for STOP (P)
Condition
tSU, STO
160
ns
Capacitive Load for Each Bus
Line
CB
(Notes 13, 14)
400
pF
Pulse Width of Spike Suppressed
0
10
ns
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