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參數(shù)資料
| 型號： | MAX1364MEUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/25頁 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MON 12BIT 4CH 10-UMAX |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 133k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 444.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
MAX1363/MAX1364
Power Supply
The MAX1363 (2.7V to 3.6V) and MAX1364 (4.5V to
5.5V) operate from a single supply and consume 670A
(typ) at sampling rates up to 94.4ksps and
436A in monitor mode at 133ksps. The MAX1363
features a 2.048V internal reference, and the MAX1364
features a 4.096V internal reference. All devices can be
configured for use with an external reference from 1V to
VDD. Bypass VDD to GND using a 0.1F or greater
ceramic capacitor for best performance.
Analog-Input and Track/Hold
The MAX1363/MAX1364 analog-input architecture con-
tains an analog-input multiplexer (mux), fully differential
T/H, comparator, and a fully differential switched
capacitive digital-to-analog converter (DAC). Figure 3
shows the equivalent input circuit for the MAX1363/
MAX1364.
In single-ended mode, the analog-input mux connects
CT/H between the analog input selected by CS[3:0] and
GND (see the
Configuration/Setup Bytes (Write Cycle)
section). In differential mode, the analog-input mux
connects CT/H to the plus and minus analog inputs
selected by CS[3:0].
During the acquisition interval, the T/H switches are in
the track position, and CT/H charges to the analog-input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position, retaining the charge
on CT/H as a stable sample of the input signal.
During the conversion, a switched capacitive DAC
adjusts to restore the comparator input voltage to 0V
within the limits of 12-bit resolution. This action requires
12 conversion clock cycles and is equivalent to trans-
ferring a charge of 11pF x (VIN+ - VIN-) from CT/H to the
binary-weighted capacitive DAC, forming a digital rep-
resentation of the analog-input signal.
Use a low source impedance to ensure an accurate
sample. A source impedance of up to 1.5kΩ does not
significantly degrade sampling accuracy. For larger
source impedances, connect a 100pF capacitor from
the analog input to GND or buffer the input.
In internal clock mode, the T/H circuitry enters track
mode on the eighth rising clock edge of the address
byte (see the
Slave Address section). The T/H circuitry
enters hold mode on the falling clock edge of the
acknowledge bit of the address byte (the ninth clock
pulse). The conversions are then internally clocked, dur-
ing which time the MAX1363/MAX1364 hold SCL low.
In external clock mode, the T/H circuitry enters track
mode after a valid address on the rising edge of the
clock during the read bit (R/
W = 1). Hold mode is
entered on the rising edge of the second clock pulse
during the shifting out of the 1st byte of the result. The
next 12 clock cycles perform the conversions.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ ≥ 9 x (RSOURCE + RIN) x CIN
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
10
______________________________________________________________________________________
TR
A
C
K
TR
A
C
K
H
O
LD
CT/H
TR
A
C
K
TRACK
H
O
LD
AIN0
AIN1
AIN2
AIN3/REF
GND
ANALOG-INPUT MUX
CAPACITIVE
DAC
REF
CAPACITIVE
DAC
REF
MAX1363
MAX1364
H
O
LD
HOLD
TRACK
HOLD
VDD/2
Figure 3. Equivalent Input Circuit
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