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參數(shù)資料
| 型號(hào)： | MAX1333 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 18-Bit Bus-Interface D-Type Latches With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 3Msps/2Msps、5V/3V、雙通道、真差分12位ADC |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 379K |
| 代理商： | MAX1333 |
M
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
_______________________________________________________________________________________
7
TIMING CHARACTERISTICS (MAX1333) (Figure 4)
(AV
DD
= +2.7V to +3.6V, DV
DD
= +2.7V to AV
DD
, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
t
CP
t
CPW
t
CRDD
t
CFDE
t
CHCF
t
BUCF
t
CFCH
t
CFBU
t
DHOLD
t
DOT
t
SETUP
t
HOLD
t
CSW
CONDITIONS
MIN
31.2
10
15
15
50
50
0
0
1
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Clock Period
SCLK Pulse Width
CNVST Rise to DOUT Disable
CNVST Fall to DOUT Enable
CHSEL to CNVST Fall Setup
BIP/
UNI
to CNVST Fall Setup
CNVST Fall to CHSEL Hold
SCLK Fall to BIP/
UNI
Hold
DOUT Remains Valid After SCLK
SCLK Rise to DOUT Transition
CNVST to SCLK Rise
SCLK Rise to CNVST
CNVST Pulse Width
C
LOAD
= 0pF (Note 4)
C
LOAD
= 30pF
2
6
6
0
6
Minimum Recovery Time (Full
Power-Down)
t
FPD
From CNVST fall or
SHDN
rise
4
μs
Minimum Recovery Time (Partial
Power-Down)
t
PPD
From CNVST fall
500
ns
Note 3:
Tested with AV
DD
= DV
DD
= +2.7V.
Note 4:
Guaranteed by design, not production tested.
DGND
6k
30pF
DOUT
a) HIGH IMPEDANCE TO V
OH
,
V
OL
TO V
OH
,
AND V
OH
TO HIGH IMPEDANCE
6k
30pF
DOUT
DGND
DV
DD
b) HIGH IMPEDANCE TO V
,
V
OH
TO V
OL
,
AND V
OL
TO HIGH IMPEDANCE
Figure 1. Load Circuits for Enable/Disable Times
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| MAX1333ETE | 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs |
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