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參數(shù)資料
| 型號： | MAX1333 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 18-Bit Bus-Interface D-Type Latches With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 3Msps/2Msps、5V/3V、雙通道、真差分12位ADC |
| 文件頁數(shù)： | 19/25頁 |
| 文件大?。?/td> | 379K |
| 代理商： | MAX1333 |
the bus master, not the MAX1332/MAX1333.)
Conversion begins with a CNVST falling edge. DOUT
goes low, indicating a conversion is in progress. Two
consecutive 1-byte reads are required to get the full 12
bits from the ADC. DOUT transitions on SCLK rising
edges and is guaranteed to be valid t
DOT
later and
remain valid until t
DHOLD
after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0 or CPOL =
1 and CPHA = 1, the data is clocked into the μC on the
following or next SCLK rising edge. When using CPOL
= 0 and CPHA = 1 or CPOL = 1 and CPHA = 0, the
data is clocked into the μC on the next falling edge.
See
Figure 11 for connections and Figures 12 and 13
for timing. See the
Timing Characteristics
table to deter-
mine the best mode to use.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows acquiring
the conversion data with a single 16-bit transfer. The
MAX1332/MAX1333 require 16 clock cycles from the
μC to clock out the 12 bits of data. Figure 14 shows a
transfer using CPOL = 1 and CPHA = 1. The conver-
sion result contains three zeros, followed by the 12 data
bits and a trailing zero with the data in MSB-first format.
DSP Interface to the TMS320C54_
The MAX1332/MAX1333 can be directly connected to
the TMS320C54_ family of DSPs from Texas
Instruments. Set the DSP to generate its own clocks or
use external clock signals. Use either the standard or
buffered serial port. Figure 15 shows the simplest inter-
face between the MAX1332/MAX1333 and the
TMS320C54_, where the transmit serial clock (CLKX)
drives the receive serial clock (CLKR) and SCLK, and
the transmit frame sync (FSX) drives the receive frame
sync (FSR) and CNVST.
For continuous conversion, set the serial port to trans-
mit a clock and pulse the frame sync signal for a clock
period before data transmission. Use the serial port
configuration (SPC) register to set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
This setup allows continuous conversions provided that
the data transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternately, autobuffering can be enabled when using
the buffered serial port to execute conversions and
read the data without μC intervention. Connect DV
DD
to
the TMS320C54_ supply voltage. The word length can
be set to 8 bits with FO = 1 to implement the power-
down modes. The CNVST pin must idle high to remain
in either power-down state.
Another method of connecting the MAX1332/MAX1333
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16 where serial clock (CLOCK) drives the
receive serial clock (CLKR) and SCLK, and the convert
signal (CONVERT) drives the receive frame sync (FSR)
and CNVST.
The serial port must be set up to accept an external
receive clock and external receive frame sync. Write
the serial port configuration (SPC) register as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion provided that
the data-receive register (DRR) is serviced before the
next conversion. Alternately, autobuffering can be
M
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
______________________________________________________________________________________
19
CNVST
SCLK
+3V TO +5V
DOUT
I/O
SCK
MISO
a) SPI
SS
MAX1332
MAX1333
CNVST
SCLK
DOUT
I/O
SK
SI
c) MICROWIRE
MAX1332
MAX1333
CNVST
SCLK
+3V TO +5V
DOUT
CS
SCK
MISO
b) QSPI
SS
MAX1332
MAX1333
Figure 11. Common Serial-Interface Connections to the
MAX1332/MAX1333
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