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參數(shù)資料
| 型號： | MAX1333 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 18-Bit Bus-Interface D-Type Latches With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 3Msps/2Msps、5V/3V、雙通道、真差分12位ADC |
| 文件頁數(shù)： | 15/25頁 |
| 文件大小： | 379K |
| 代理商： | MAX1333 |
modes, the input common-mode voltage can vary as
long as the voltage at any single analog input (V
AIN_P
,
V
AIN_N
) remains within 50mV of the analog power sup-
ply rails (AV
DD
, AGND).
As shown in
Figure 3, internal protection diodes confine
the analog input voltage within the region of the analog
power-supply rails (AV
DD
, AGND) and allow the analog
input voltage to swing from AGND - 0.3V to AV
DD
+ 0.3V
without damage. Input voltages beyond AGND - 0.3V
and AV
DD
+ 0.3V forward bias the internal protection
diodes. In this situation, limit the forward diode current to
50mA to avoid damaging the MAX1332/MAX1333.
Serial Digital Interface
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. CNVST
controls the state of the T/H as well as when a conver-
sion is initiated. CNVST also controls the power-down
mode of the device (see the
Partial Power-Down (PPD)
and Full Power-Down (FPD) Mode
section). SCLK
clocks data out of the serial interface and sets the con-
version speed. Figures 4 and 5 show timing diagrams
that outline the serial-interface operation.
Starting a Conversion
On power-up, the MAX1332/MAX1333 enter full power-
down mode. The first rising edge of CNVST exits the full
power-down mode and the MAX1332/MAX1333 begin
acquiring the analog input. A CNVST falling edge initi-
input voltage; DOUT changes from high impedance to
logic low; and the ADC begins to convert at the first
SCLK rising edge. SCLK is used to drive the conver-
sion process, and it shifts data out of DOUT. SCLK
begins shifting out the data after the 4th rising edge of
SCLK. DOUT transitions t
DOT
after each SCLK’s rising
edge and remains valid for t
DHOLD
after the next rising
edge. The 4th rising clock edge produces the MSB of
the conversion result at DOUT, and the MSB remains
valid t
DHOLD
after the 5th rising edge of SCLK. Sixteen
M
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
______________________________________________________________________________________
15
D11
0
0
0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
SCLK
CNVST
0
POWER- MODE SELECTION WINDOW
HOLD
TRACK
ANALOG
INPUT TRACK
AND HOLD STATE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
t
ACQ
HIGH-Z
t
SETUP
t
CONV
CONTINUOUS-CONVERSION
SELECTION WINDOW
Figure 5. Interface Timing Sequence
CNVST
SCLK
DOUT
t
SETUP
t
CFDE
t
CP
t
CRDD
t
DOT
t
DHOLD
t
HOLD
t
CSW
Figure 4. Detailed Serial-Interface Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX1333ETE | 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs |
| MAX1332ETE | 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs |
| MAX135EPI | 15-Bit ADC with Parallel Interface |
| MAX135EWI | 15-Bit ADC with Parallel Interface |
| MAX135 | Dual 8-Bit To 9-Bit Parity Transceivers 56-SSOP -40 to 85 |
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