參數(shù)資料
型號: MAX11210EEE+T
廠商: Maxim Integrated Products
文件頁數(shù): 6/27頁
文件大小: 0K
描述: ADC 24BIT 4WIRE SPI 16-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 24
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 667mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極;1 個差分,雙極
14
Maxim Integrated
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
MAX11200/MAX11210
Figure 5. SPI Command Byte
Figure 6. SPI Register Access Write
Figure 7. SPI Register Access Read
Serial-Digital Interface
The MAX11200/MAX11210 interface is fully compatible
with SPI-, QSPI-, and MICROWIRE-standard serial inter-
faces. The SPI interface provides access to nine on-chip
registers that are 8 or 24 bits wide.
Drive CS low to transfer data in and out of the devices.
Clock in data at DIN on the rising edge of SCLK. The
RDY/DOUT output serves two functions: conversion sta-
tus and data read. To find the conversion status, assert
CS low and read the RDY/DOUT output; the conversion
is in progress if the RDY/DOUT output reads logic-high
and the conversion is complete if the RDY/DOUT output
reads logic-low. Data at RDY/DOUT changes on the
falling edge of SCLK and is valid on the rising edge of
SCLK. DIN and DOUT are transferred MSB first. Drive
CS high to force DOUT high impedance and cause the
devices to ignore any signals on SCLK and DIN. Figures
5, 6, and 7 show the SPI timing diagrams.
tCSH0
tDOE
HIGH-Z
tDOD
HIGH-Z
tCSS0
SCLK
0
X
1
10
CAL1
CAL0
IMPD
RATE2
RATE1
RATE0
8
DIN
tDH
tCP
tCSH1
tCSS1
tCSW
tCL tCH
tDS
CS
RDY/DOUT
tCSH0
tDOE
HIGH-Z
tDOD
HIGH-Z
tCSS0
SCLK
0
X
1
11
X
RS3
RS2
RS1
RS0
W/R
D7
D6
D5
D4
D3
D2
D1
D0
16
89
DIN
tDH
tCP
tCSH1
tCSS1
tCSW
tCL
tCH
tDS
CS
RDY/DOUT
tDOE
HIGH-Z
SCLK
X
1
11
X
RS3
RS2
RS1
RS0
W/R
XX
X
XXX
XX
D6
D7
D5
D4
D3
D2
D1
D0
16
89
DIN
tCP
tDOD
tDOT
tDO1
tDOH
CS
RDY/DOUT
tCSS0
tDS
tCSS1
tCL
tCH
tDH
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