參數(shù)資料
型號： MAX11210EEE+T
廠商： Maxim Integrated Products
文件頁數(shù)： 15/27頁
文件大小： 0K
描述： ADC 24BIT 4WIRE SPI 16-QSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
位數(shù)： 24
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 667mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，單極；1 個差分，雙極
22
Maxim Integrated
24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
MAX11200/MAX11210
Table 16b. Output Data Formats for the Bipolar Input Range
Table 17. SOC Register (Read/Write)
SOC: System Offset Calibration Register
The system offset calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB (most significant bit) first. This register holds the system offset calibration value. The format is always in
two’s complement binary format. A write to the system-calibration register is allowed. The value written remains valid
until it is either rewritten or until an on-demand system-calibration operation is performed, which overwrites the user-
supplied value.
The system offset calibration value is subtracted from each conversion result provided the NOSYSO bit in the CTRL3
register is set to 0. The system offset calibration value is subtracted from the conversion result after self-calibration
but before system gain correction. The system offset calibration value is also applied prior to the 1x or 2x scale factor
associated with bipolar and unipolar modes.
BIT
B23
B22
B21
B20
B19
B18
B17
B16
DEFAULT
0
BIT
B15
B14
B13
B12
B11
B10
B9
B8
DEFAULT
0
BIT
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0
INPUT VOLTAGE
VAINP - VAINN
DIGITAL OUTPUT CODE FOR BIPOLAR RANGES
OFFSET BINARY FORMAT
TWO’S COMPLEMENT FORMAT
≥ VREF
0xFFFFFF
0x7FFFFF
REF
23
1
V1
21
×
0xFFFFFE
0x7FFFFE
REF
23
V
21
0x800001
0x000001
0
0x800000
0x000000
REF
23
V
21
0x7FFFFF
0xFFFFFF
REF
23
1
V1
21
×
0x000001
0x800001
≤ -VREF
0x000000
0x800000
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