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參數(shù)資料
| 型號： | M8761ED |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 24BIT 192KHZ STEREO DAC |
| 中文描述： | 24位192kHz的立體聲DAC |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 223K |
| 代理商： | M8761ED |
WM8761
Production Data
w
PD Rev 4.0 May 2004
8
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MCLK Master clock pulse width high
t
MCLKH
t
MCLKL
t
MCLKY
8
8
20
40:60
1.5
ns
ns
ns
μ
s
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
60:40
12
Time from MCLK stopping to power
down.
DIGITAL AUDIO INTERFACE
BCKIN
LRCIN
t
BCH
t
BCL
t
BCY
DIN
t
LRSU
t
DS
t
LRH
t
DH
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCKIN cycle time
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
LRCIN hold time from
BCKIN rising edge
DIN set-up time to BCKIN
rising edge
DIN hold time from BCKIN
rising edge
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
BCY
t
BCH
t
BCL
t
LRSU
40
16
16
8
ns
ns
ns
ns
t
LRH
8
ns
t
DS
8
ns
t
DH
8
ns
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