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參數(shù)資料
| 型號： | M8761ED |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 24BIT 192KHZ STEREO DAC |
| 中文描述： | 24位192kHz的立體聲DAC |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 223K |
| 代理商： | M8761ED |
WM8761
Production Data
w
PD Rev 4.0 May 2004
12
Figure 5 DSP ‘Late’ Mode Timing
Figure 6 DSP ‘Early’ Mode Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8761 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8761 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCIN, although the WM8761 is tolerant of phase
differences or jitter on this clock.
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
SAMPLING
RATE
(LRCIN)
32kHz
44.1kHz
48kHz
96kHz
192kHz
Table 1 Master Clock Frequencies Versus Sampling Rate
128fs
192fs
256fs
384fs
512fs
768fs
4.096
5.6448
6.144
12.288
24.576
6.144
8.467
9.216
18.432
36.864
8.192
11.2896
12.288
24.576
Unavailable Unavailable Unavailable Unavailable
12.288
16.9344
18.432
36.864
16.384
22.5792
24.576
Unavailable Unavailable
24.576
33.8688
36.864
LRCIN
BCKIN
DIN
Input Word Length (16 bits)
1/fs
LEFT CHANNEL
16
2
1
15
LSB
MSB
16
2
1
15
RIGHT CHANNEL
NO VALID DATA
1
Max 4 BCKIN's
LRCIN
BCKIN
DIN
Input Word Length (16 bits)
1/fs
LEFT CHANNEL
16
2
1
15
LSB
MSB
16
2
1
15
RIGHT CHANNEL
NO VALID DATA
1 BCKIN
1 BCKIN
max 4 BCKIN's
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