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參數(shù)資料
| 型號： | M8761ED |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 24BIT 192KHZ STEREO DAC |
| 中文描述： | 24位192kHz的立體聲DAC |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 223K |
| 代理商： | M8761ED |
WM8761
Production Data
w
PD Rev 4.0 May 2004
10
Typically an external low pass filter circuit will be used to remove residual out of band noise
characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8761
produces far less out of band noise than single bit traditional sigma delta DACs, and so in many
applications this filter may be removed, or replaced with a simple RC pole.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock
to which all audio data processing is synchronised. This clock is often referred to as the audio
system’s Master Clock. The external master clock can be applied directly through the MCLK input
pin with no configuration necessary for sample rate selection.
Note that on the WM8761, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In
a system where there are a number of possible sources for the reference clock it is recommended
that the clock source with the lowest jitter be used to optimise the performance of the DAC.
The device can be powered down by stopping MCLK. In this state the power consumption is
substantially reduced.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface
formats are supported:
Right Justified mode
I
2
S mode
DSP mode
All formats send the MSB first. The data format is selected with the FORMAT pin. When
FORMAT is LOW, right justified data format is selected and word lengths up to 24-bits may be
used. When the FORMAT pin is HIGH, I
S format is selected and word length of any value up to
24-bits may be used. (If a word length shorter than 24-bits is used, the unused bits will be padded
with zeros). If LRCIN is 4 BCKINs or less duration, the DSP compatible format is selected. Early
and Late clock formats are supported, selected by the state of the FORMAT pin.
‘Packed’ mode (i.e. only 32 or 48 clocks per LRCIN period) operation is also supported in I
2
S and
right justified modes. If a ‘packed’ format of 16-bit word length is applied (16 BCKINS per LRCIN
half period), the device auto-detects this mode and switches to 16-bit data length.
I
2
S MODE
The WM8761 supports word lengths of 16-24 bits in I
2
S mode.
In I
2
S mode, the digital audio interface receives data on the DIN input. Audio Data is time
multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used
as a timing reference to indicate the beginning or end of the data words.
In I
2
S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word
length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word
length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements
are met. In I
S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left samples and high during the right samples.
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