參數(shù)資料
型號(hào)： M80XXLFXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： OTHER CLOCK GENERATOR, QCC24
封裝： 4 X 4 MM, LEAD FREE, MO-220, QFN-24
文件頁數(shù)： 2/17頁
文件大?。?/td> 526K
代理商： M80XXLFXI
MoBL Clock
M4000/M8000
Document Number: 001-29179 Rev. *C
Page 10 of 17
DC Electrical Specifications
DC Electrical Specification table for MoBL Clock M40xx/M80xx family (VDD_CLK_BX = 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V)
Parameter
Description
Conditions
Min
Typ
Max
Unit
VOL
Output Low Voltage, CLK pins
IOL = 2 mA, drive strength = [00]
–
0.4
V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH
Output High Voltage, CLK pins
IOH = –2 mA, drive strength = [00]
VDD_CLK_BX
– 0.4
––
V
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VOLSD
Output Low Voltage, SDA
IOL = 4 mA
–
0.4
V
VIL1
Input Low Voltage of SSON,
PD#/OE, SDA and SCL pins
–
0.2*VDD
V
VIL2
Input Low Voltage of EXCLKIN
pin
–
0.15
V
VIH1
Input High Voltage of SSON,
PD#/OE, SDA and SCL pins
0.8*VDD
––
V
VIH2
Input High Voltage of EXCLKIN
pin
1.6
–
2.2
V
IIL1
Input Low Current, PD#/OE pin VIL = 0 V
–
10
A
IIH1
Input High Current, PD#/OE pin VIH = VDD
––
10
A
IIL2
Input Low Current, SSON pin
VIL = 0V (Internal pull down resistor
= 160k typ.)
––
10
A
IIH2
Input High Current, SSON pin
VIH = VDD (Internal pull down resistor
= 160k typ.)
14
–
36
A
RDN
Pull Down Resistor of clocks
(CLK1-CLK8) in off-state
Clock outputs in off-state by setting
PD# = Low
100
160
250
k
IDD[1, 2]
Supply Current
All outputs running, CLOAD = 0
–
15
–
mA
IDDS[1]
Standby Current
PD# = Low, and
I2C circuit not in Keep
Alive Mode
–3
–
A
CIN[2]
Input Capacitance
SCL, SDA, SSON and PD#/OE
inputs
––
7
pF
Notes
1. This parameter is configuration dependent. The specified value is for the drive level setting of [1,1].
2. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
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