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參數(shù)資料
| 型號： | M80XXLFXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC24 |
| 封裝： | 4 X 4 MM, LEAD FREE, MO-220, QFN-24 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 526K |
| 代理商： | M80XXLFXI |
MoBL Clock
M4000/M8000
Document Number: 001-29179 Rev. *C
Page 5 of 17
General Description
4 Configurable PLLs
The MoBL Clock M4000/M8000 family of products are four-PLL
Clock Generator ICs designed for cell phone, portable, or
consumer electronics applications. It can be used to generate
four independent output frequencies ranging from 3 to 50 MHz
from a single input reference clock.
I2C Programming
The MoBL Clock, M4000 and M8000 have a serial I2C interface
that programs the configuration memory array to synthesize
output frequencies by programmable output divider, spread
characteristics, and drive strength. I2C can also be used for
in-system control of these programmable features.
Input Reference Clocks
The input to the M4000 and M8000 can be either a crystal or a
clock signal. The input frequency range for crystals is 8 MHz to
48 MHz, while that for EXCLKIN is 1 to 48 MHz. The voltage level
for the input reference clock used must meet the voltage
requirement for the device as shown in the DC and AC
specifications.
Output Power Supply Options
These devices have eight clock outputs grouped in three banks.
The Bank 1, Bank 2, and Bank 3 correspond to (CLK1, CLK2),
(CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8) respectively. A
separate power supply is used for each of these three output
drivers and they can be any of 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V
giving user multiple choice of output clock voltage levels.
Output Source Selection
These devices have eight clock outputs (CLK1–8). There are five
available clock sources for these outputs. These clock sources
are: XIN/EXCLKIN, PLL1, PLL2, PLL3 and PLL4. Output clock
source selection is done using four out of five crossbar switch.
Thus, any one of these five available clock sources can be
arbitrarily selected for the clock outputs. This gives user a
flexibility to have up to four independent clock and a reference
clock outputs.
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and Spread Spectrum Clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off by I2C
device programming. It can be factory programmed to either
center spread range from ±0.125% to ±2.50%, or down spread
range from –0.25% to –5.0%, with Lexmark or Linear modulation
profile.
PD#/OE Mode
PD#/OE input (Pin 4) can be programmed to operate as either
power down (PD#) or output enable (OE) mode. Note that power
down shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings. The
PD# turn-on time is limited by the turn-on time of the PLLs.
Disabled outputs are first driven to a low state before turning off.
When off, they are held low by internal weak resistors
(~160 k ohms)
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 4). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Keep Alive Mode
By activating the device in the Keep Alive Mode, power down
mode is changed to power saving mode, which disables all PLLs
and outputs, but preserves the contents of the volatile registers.
Thus, any configuration changes made via the I2C interface are
preserved. By deactivating the Keep Alive Mode, I2C memory is
not preserved during power down, but power consumption is
reduced relative to the Keep Alive Mode.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 3 shows the typical rise
and fall times for different drive strength settings.
Factory Specific Configuration and Custom
Programming
The device is available with Factory Specific programmed
frequencies as shown in the Ordering Information page. This
factory specific programmed part can be used for the device
evaluation purposes. The MoBL Clock can be custom
programmed to any desired frequencies and listed features. For
customer specific programming and I2C programmable memory
bitmap definitions, please contact local Cypress Field Appli-
cation Engineer (FAE) or sales representative.
Table 3. Output Drive Strength
Output Drive Strength
Rise/Fall Time (ns)
(Typical Value)
Low
6.8
Mid Low
3.4
Mid High
2.0
High
1.0
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