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參數(shù)資料
| 型號： | M6MGT160S4BVP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-MCP |
| 中文描述： | 3.3的CMOS只快閃記憶體 |
| 文件頁數(shù)： | 25/30頁 |
| 文件大?。?/td> | 257K |
| 代理商： | M6MGT160S4BVP |
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MITSUBISHI LSIs
Sep. 1999 , Rev.2.0
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
M6MGB/T160S4BVP
When setting BYTE# at the low level and other pins are in
anactive stage , lower-byte I/O are in a selesctable mode in
whichboth reading and writing are enabled, and upper-byte are
in anon-selectable mode.
When setting S-CE at a low level,the chips are in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in ahigh-impedance
state, allowing OR-tie with other chips and memory expansion
by S-CE.
The power supply current is reduced as low as 0.3
m
A(25
C,typical), and the memory data can be held at +2V
powersupply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
The SRAM of M6MGB/T160S4BVP is organized as
262,144-word by 16-bit/ 524,288-word by 8-bit. These
devices operate on a single +2.7~3.6V powersupply, and are
directly TTL compatible to both input and output. Its fully
static circuit needs no clocks and no refresh, and makes it
useful.
The operation mode are determined by a combination of
the device control inputs BYTE#, S-CE , WE# and OE#.
Each mode is summarized in the function table.
A write operation is executed whenever the low level WE#
overlaps with the high level S-CE. The address(A-1~A17:byte
mode, A0~A17:word mode) must be set up before the write
cycle and must be stable during the entire cycle.
A read operation is executed by setting WE# at a high level
and OE# at a low level while S-CE are in an active
state(S-CE=H).
2. SRAM
25
FUNCTION TABLE
Mode
WE#
X
L
H
H
L
H
X
H
H
H
L
L
High-Z
Din
Dout
High-Z High-Z
Din
Dout
BYTE#
OE#
X
X
L
H
X
L
H
DQ0~7
Non selection
Write
DQ8~15
High-Z Standby
Din
Dout
Icc
Active
Active
Active
Active
Active
Read
L
Active
High-Z
H
High-Z
Write
Read
High-Z
High-Z
S-CE
L
H
H
H
H
H
H
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