參數(shù)資料
型號: M6MGT160S4BVP
廠商: Mitsubishi Electric Corporation
英文描述: CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-MCP
中文描述: 3.3的CMOS只快閃記憶體
文件頁數(shù): 14/30頁
文件大小: 257K
代理商: M6MGT160S4BVP
MITSUBISHI LSIs
Sep. 1999 , Rev.2.0
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
M6MGB/T160S4BVP
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
ADDRESSES
(A
0
- A
19
,A
-1
*)
ADDRESS VALID
F-CE#
BYTE#
DATA
(D
0
- D
7
)
BYTE AC WAVEFORMS FOR READ OPERATION
t
a(AD)
HIGH-Z
V
IH
V
IL
DATA
(D
8
- D
14
)
HIGH-Z
V
IH
V
IL
D
15
/ A
-1
t
a(BYTE)
t
BHZ
VALID
VALID
OUTPUT VALID
VALID
A
-1
D
15
A
-1
V
IH
V
IL
OE#
When BYTE#=V
IH
, F-CE#=OE#=V
IL
, D
15
/A
-1
is output status. At this time, input signal must not be applied.
ADDRESS VALID
t
a(AD)
t
a(CE)
t
a(OE)
t
a(BYTE)
t
OLZ
t
BCD
t
BAD
t
CLZ
t
BAD
t
OH
t
DF(OE)
t
DF(CE)
14
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
OUTPUT VALID
HIGH-Z
t
DF(OE)
t
RC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
ADDRESSES
F-CE#
OE#
WE#
DATA
ADDRESS VALID
t
OH
t
OLZ
t
a (CE)
t
RE
t
CLZ
t
a (AD)
t
a (OE)
HIGH-Z
V
IH
V
IL
F-RP#
t
PS
t
DF(CE)
t
PHZ
Valid
FFH or 71H
In the case of use F-CE# is Low fixed, it is allowed to define a timming specification of tRE
from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE).
(This is only for FFH,71H program and read)
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