參數(shù)資料
型號: M58LT128GST1ZA5E
廠商: 意法半導體
英文描述: 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
中文描述: 128Mbit(8兆x16插槽,多銀行,多層次,多突發(fā))1.8V電源安全閃存
文件頁數(shù): 62/98頁
文件大?。?/td> 693K
代理商: M58LT128GST1ZA5E
11 DC and AC parameters
M58LT128GST, M58LT128GSB
62/98
Table 24.
Write AC Characteristics, Write Enable Controlled
Symbol
Alt
Parameter
(1)
1.
Sampled only, not 100% tested.
M58LT128GST,
M58LT128GSB
Unit
110
W
t
AVAV
t
WC
Address Valid to Next Address Valid
Min
110
ns
t
AVLH
Address Valid to Latch Enable High
Min
11
ns
t
AVWH(2)
2.
These timings are meaningful only if Latch Enable, L, is always kept Low, V
IL
.
t
has the values shown when reading in the targeted bank. System designers should take this into account and may
insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array
operation in a different bank t
WHEL
is 0ns.
Address Valid to Write Enable High
Min
50
ns
t
DVWH
t
DS
Data Valid to Write Enable High
Min
50
ns
t
ELLH
Chip Enable Low to Latch Enable High
Min
11
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
Min
0
ns
t
ELQV
Chip Enable Low to Output Valid
Min
110
ns
t
ELKV
Chip Enable Low to Clock Valid
Min
9
ns
t
GHWL
Output Enable High to Write Enable Low
Min
17
ns
t
LHAX
Latch Enable High to Address Transition
Min
9
ns
t
LLLH
Latch Enable Pulse Width
Min
11
ns
t
WHAV(2)
Write Enable High to Address Valid
Min
0
ns
t
WHAX(2)
Write Enable High to Address Transition
Min
0
ns
t
WHDX
t
DH
Write Enable High to Input Transition
Min
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
Min
0
ns
t
WHEL(3)
3.
Write Enable High to Chip Enable Low
Min
25
ns
t
WHLL
Write Enable High to Latch Enable Low
Min
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
Min
25
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
Min
50
ns
P
t
QVVPL
Output (Status Register) Valid to V
PP
Low
Min
0
ns
t
VPHWH
t
VPS
V
PP
High to Write Enable High
Min
200
ns
t
WHVPL
Write Enable High to V
PP
Low
Min
200
ns
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