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參數(shù)資料
| 型號： | M58LT128GST1ZA5E |
| 廠商： | 意法半導體 |
| 英文描述： | 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories |
| 中文描述： | 128Mbit（8兆x16插槽，多銀行，多層次，多突發(fā)）1.8V電源安全閃存 |
| 文件頁數(shù)： | 16/98頁 |
| 文件大?。?/td> | 693K |
| 代理商： | M58LT128GST1ZA5E |
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3 Bus operations
M58LT128GST, M58LT128GSB
16/98
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus Write,
Address Latch, Output Disable, Standby and Reset. See
Table 3: Bus Operations
, for a
summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory
and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output
Enable must be at V
IL
in order to perform a read operation. The Chip Enable input should be
used to enable the device. Output Enable should be used to gate data onto the output. The
data read depends on the previous command written to the memory (see Command Interface
section). See
Figure 9
,
Figure 11
and
Figure 12
Read AC Waveforms, and
Table 22
and
Table 23
Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write Commands to the memory or latch Input Data to be programmed. A
bus write operation is initiated when Chip Enable and Write Enable are at V
IL
with Output
Enable at V
IH
. Commands, Input Data and Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the
write operation by toggling Latch Enable. In this case the Latch Enable should be tied to V
IH
during the bus write operation. See
Figure 15
and
Figure 16
, Write AC Waveforms, and
Table 24
and
Table 25
, Write AC Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at
V
IL
during address latch operations. The addresses are latched on the rising edge of Latch
Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at V
IH
.
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at V
IH
. The power
consumption is reduced to the standby level I
DD3
and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V
IH
during a program or erase operation, the device enters Standby mode when finished.
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| M58LT128HSB8ZA6E | 功能描述:IC FLASH 128MBIT 85NS 64TBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
| M58LT128HSB8ZA6F | 功能描述:IC FLASH 128MBIT 85NS 64TBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
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