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參數(shù)資料
| 型號： | M50FLW080BN5G |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 |
| 封裝： | 10 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-40 |
| 文件頁數(shù)： | 11/64頁 |
| 文件大小： | 534K |
| 代理商： | M50FLW080BN5G |
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M50FLW080A, M50FLW080B
Bus operations
3.2
Address/Address multiplexed (A/A Mux) bus operations
The Address/Address Multiplexed (A/A Mux) Interface has a more traditional-style interface.
The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash
Programming equipment for faster factory programming. Only a subset of the features
available to the Firmware Hub (FWH)/Low Pin Count (LPC) Interface are available; these
include all the Commands but exclude the Security features and other registers.
The following operations can be performed using the appropriate bus cycles: Bus Read, Bus
Write, Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux) Interface is selected, all the blocks are
unprotected. It is not possible to protect any blocks through this interface.
3.2.1
Bus Read
Bus Read operations are used to read the contents of the Memory Array, the Electronic
Signature or the Status Register. A valid Bus Read operation begins by latching the Row
Address and Column Address signals into the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Write Enable (W) and Interface Reset (RP) must
be High, VIH, and Output Enable, G, Low, VIL. The Data Inputs/Outputs will output the value,
according to the timing constraints specified in Figure 16, and Table 28.
3.2.2
Bus Write
Bus Write operations are used to write to the Command Interface. A valid Bus Write
operation begins by latching the Row Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The
data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset,
RP, must be High, VIH; and Write Enable, W, must be Low, VIL. The Data Inputs/Outputs are
latched on the rising edge of Write Enable, W. See Figure 17, and Table 29, for details of the
timing requirements.
3.2.3
Output Disable
The data outputs are high-impedance when the Output Enable, G, is at VIH.
3.2.4
Reset
During the Reset mode, all internal circuits are switched off, the device is deselected, and
the outputs are put at high-impedance. The device is in the Reset mode when RP is Low,
VIL. RP must be held Low, VIL for tPLPH. If RP goes Low, VIL, during a Program or Erase
operation, the operation is aborted, and the affected memory cells no longer contain valid
data. The memory can take up to tPLRH to abort a Program or Erase operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50FLW080BN5P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BN5TG | 功能描述:IC FLASH 8MBIT 33MHZ 40TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| M50FLW080BN5TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080BNB5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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