參數(shù)資料
型號: M393B5773CH0-CK0
元件分類: DRAM
英文描述: 256M X 72 MULTI DEVICE DRAM MODULE, 0.225 ns, DMA240
封裝: HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
文件頁數(shù): 21/58頁
文件大?。?/td> 1982K
代理商: M393B5773CH0-CK0
- 22 -
datasheet
DDR3 SDRAM
Rev. 1.0
Registered DIMM
14. AC & DC Output Measurement Levels
14.1 Single Ended AC and DC Output Levels
[ Table 8 ] Single Ended AC and DC output levels
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25
Ω to VTT=VDDQ/2.
14.2 Differential AC and DC Output Levels
[ Table 9 ] Differential AC and DC output levels
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25
Ω to VTT=VDDQ/2 at each of the differential outputs.
14.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
[ Table 10 ] Single ended Output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 11 ] Single ended output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
Figure 6. Single-ended output slew rate definition
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC) DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC) DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC) AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V1
VOL(AC) AC output low measurement level (for output SR)
VTT - 0.1 x VDDQ
V1
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V1
Description
Measured
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
VOH(AC)-VOL(AC)
Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
VOH(AC)-VOL(AC)
Delta TFse
Parameter
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Min
Max
Min
Max
Min
Max
Min
Max
Single ended output slew rate
SRQse
2.5
5
2.5
5
2.5
5
TBD
5
V/ns
VOHdiff(AC)
VOLdiff(AC)
delta
TRdiff
delta
TFdiff
VTT
相關(guān)PDF資料
PDF描述
M3950/1529A012 TOGGLE SWITCH, 3PDT, LATCHED, 4A, 28VDC, THROUGH HOLE-STRAIGHT
M83731/2327D110 TOGGLE SWITCH, 3PDT, MOMENTARY, 4A, 28VDC, THROUGH HOLE-STRAIGHT
M3950/1726A110 TOGGLE SWITCH, 3PDT, LATCHED, 4A, 28VDC, THROUGH HOLE-STRAIGHT
M3E-R21ZQXFREQ CRYSTAL OSCILLATOR, CLOCK, 1.5 MHz - 155.52 MHz, PECL OUTPUT
M3E73XPD-RFREQ CRYSTAL OSCILLATOR, CLOCK, 1.5 MHz - 155.52 MHz, PECL OUTPUT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M393B5773DH0-CH908 制造商:Samsung Semiconductor 功能描述:
M393T1G60CJA-CE6 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE
M393T1G60QJMA 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 SDRAM Memory
M393T1K66AZHA 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 SDRAM Memory
M393T2863AZ3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE