APPLICATION
2.5 Serial I/O1
3820 GROUP USER’S MANUAL
2–118
I
Receive operation in the UART mode
Receive operation in the UART mode is described below.
G
Start of receive operation
In the receive enable state,
8
1
set the receive enable bit (bit 5) of the serial I/O1 control register
(address 001A
16
) into the enabled state (“1”). With this operation, a start bit is detected and a
receive operation of serial data is started.
G
Receive operation
With the lapse of a 1/2 period of the shift
clock from detection of the falling of the P4
4
/
RxD pin input, the P4
4
/RxD pin level is
checked. When it is “L” level, the bit is judged
as a start bit.
When it is “H” level, the bit is judged as noise,
so the receive operation is stopped, being
put into wait status for a start bit again.
Each 1-bit data is read into the receive shift
register from the P4
4
/RxD pin in synchroni-
zation with the rising of the shift clocks.
The data after the detection of the start bit
enters first into the most significant bit of the
receive shift register. Each time 1-bit data is
received, the data of the receive shift regis-
ter is shifted by 1 bit toward the least signifi-
cant bit.
When a specified number of bits has been
input into the receive shift register, the data
of the receive shift register are transferred to
the receive buffer register (address
0018
16
).
8
2
8
3
8
1: Initialization of register or others for a receive operation. Refer to
“2.5.4 Register setting exam-
ple.”
8
2: When the data bit length is 7 bits, bits 0 to 6 of the receive buffer register are receive data, and
bit 7 (MSB) is cleared to “0.”
8
3: When data remains without reading out the data of the receive buffer register (the receive buffer
full flag is “1”) and yet all the receive data has been input to the receive shift register, the overrun
error flag of the serial I/O1 status register is set to “1.” At this time, the data of the receive shift
register is not transferred to the receive buffer register, but the former data of the receive buffer
register is held.
Shift clock
R
X
D (Noise)
R
X
D (ST)
Receive shift register
b0
D
4
P4
4
/R
X
D
D
2
D
3
D
1
D
0
Transfer receive data
[Address 18
16
]
Receive buffer register
Receive shift register
D
6
D
7
D
5
D
4
D
2
D
3
D
1
D
0
Receive shift register
P4
4
/R
X
D
D
1
b0
D
0