APPLICATION
2.3 Timer X and timer Y
3820 GROUP USER’S MANUAL
2–82
2.3.6 Notes on use
Notes on using each mode of the timer X and timer Y are described below.
(1) Timer X
I
Common to all modes
G
When reading or writing for timer X, be sure to execute for both the timer X (high-order) and the
timer X (low-order). When reading a value from the timer X, read it in the order of the timer X (high-
order) and the timer X (low-order). When writing a value to the timer X, execute in the order of the
timer X (low-order) and the timer X (high-order). If the following operations are performed for the
timer X, abnormal operation will occur.
Write operation before execution of timer X (low-order) reading
Read operation before execution of timer X (high-order) writing
In writing for the latch only (timer X write control bit = “1”), if writing timing for the high-order latch
is almost same as the underflow timing, a normal value may not be set in the high-order counter.
I
Pulse output mode
G
In the pulse output mode, set the bit 4 (corresponding to the P5
4
/CNTR
0
) of the port P5 direction
register (address 000B
16
) to “1” (output mode).
G
When the bit 4 (corresponding to the P5
4
/CNTR
0
) of the port P5 register (address 000A
16
) in the
pulse output mode is read, the value of the port register are not read out but the output value of
the pin is read out.
I
Event counter mode
G
When using the event counter mode, set the bit 4 (corresponding to the P5
4
/CNTR
0
) of the port P5
direction register (address 000B
16
) to “0” (input mode).
G
The maximum input frequency in the event counter mode is:
4 MHz (250 ns) ..................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
(2
V
CC
) – 4 MHz ( 500
CC
= 2.5 V to 4.0 V
The minimum “H” pulse width is:
105 ns ..................................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
( 250
CC
= 2.5 V to 4.0 V
The minimum “L” pulse is:
105 ns ..................................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
( 250
CC
= 2.5 V to 4.0 V
I
Pulse width measurement mode
G
In the pulse width measurement mode, set the bit 4 (corresponding to P5
4
/CNTR
0
) of the port P5
direction register (address 000B
16
) to “0” (input mode).
G
In reading the value of the P5
4
/CNTR
0
pin as an input pin, the value is “1” at “H” level input or “0”
at “L” level input regardless of the value of the CNTR
0
active edge switch bit.
G
Setting the CNTR
0
active edge switch bit effects on the active edge of an interrupt. Consequently,
a CNTR
0
interrupt request may be caused by setting the CNTR
0
active edge switch bit.
As a countermeasure against the above, switch the active edge after disabling the CNTR
0
interrupt,
then set the CNTR
0
interrupt request bit to “0.”
G
The minimum “H” pulse width in the pulse width measurement mode is:
105 ns ..................................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
( 250
CC
= 2.5 V to 4.0 V
The minimum “L” pulse is:
105 ns ..................................................................at V
CC
= 4.0 V to 5.5 V
V
CC
– 2
( 250
CC
= 2.5 V to 4.0 V