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參數(shù)資料
| 型號： | M37905M8C-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16 BIT CMOS MICROCOMPUTER |
| 中文描述： | 16位CMOS微機 |
| 文件頁數(shù)： | 63/102頁 |
| 文件大小： | 881K |
| 代理商： | M37905M8C-XXXFP |
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63
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
succeedingly.
Once transmission has started, the TEi flag, TIi flag, and CTSi signal
are ignored until data transmission is completed.
Therefore, transmission does not stop until it completes event if, dur-
ing transmission, the TEi flag is cleared to
“
0
”
or CTSi input is set to
“
1
”
.
The transmission start condition indicated by TEi flag, TIi flag, and
CTSi is checked while the T
END
i signal shown in Figure 69 is
“
H
”
.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIi flag is
cleared to
“
0
”
before the T
END
i signal goes
“
H
”
.
Bit 3 (T
X
EPTYi flag) of UARTi transmit/receive control register 0
changes to
“
1
”
at the next cycle just after the T
END
i signal goes
“
H
”
and changes to
“
0
”
when transmission starts. Therefore, this flag can
be used to determine whether data transmission is completed.
When the TIi flag changes from
“
0
”
to
“
1
”
, the interrupt request bit of
the UARTi transmit interrupt control register is set to
“
1
”
.
Transmission
Transmission is started when bit 0 (TEi flag transmit enable flag) of
UARTi transmit/receive control register 1 is
“
1
”
, bit 1 (TIi flag) is
“
0
”
,
and CTS
i
input (in other words, transmit enable signal input from re-
ceiver) is
“
L
”
. The TIi flag indicates whether the transmit buffer is
empty or not. It is cleared to
“
0
”
when data is written in the transmit
buffer; it is set to
“
1
”
when the contents of the transmit buffer register
is transferred to the transmit register.
When all of the transmission conditions are satisfied, transmit data
is transferred to the transmit register, and transmit operation starts.
As shown in Figures 69 and 70, data is output from the T
X
Di pin with
the stop bit or parity bit specified by bits 4 through 6 of UARTi trans-
mit/receive mode register. The data is output from the least signifi-
cant bit.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmit start condi-
tion is satisfied. Then, the next transmission is performed
Fig. 71 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected
Start bit
Stop bit
Start bit
D
0
D
1
D
7
Check to be
“
L
”
level
Starting at the falling
edge of start bit
Data fetched
f
i
or f
EXT
RE
i
R
X
D
i
Receive
clock
RI
i
RTS
i
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