參數(shù)資料
型號： M37905M8C-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： 16 BIT CMOS MICROCOMPUTER
中文描述： 16位CMOS微機(jī)
文件頁數(shù)： 56/102頁
文件大小： 881K
代理商： M37905M8C-XXXFP
56
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 64 Bit configuration of UARTi transmit/receive control register
/LSB
MSB
T
X
EPTY
7
6
5
4
3
2
1
0
R/C
CS
1
CS
0
BRG count source select bits
00 : f
2
01 : f
16
10 : f
64
11 : f
512
CTS/RTS function select bit
(Note 1)
0 : CTS function is selected.
1 : RTS function is selected.
Transmit register empty flag
0 : Data is present in the transmit register. (Transmission is in progress.)
1 : No data is present in the transmit register. (Transmission is completed.)
CTS/RTS enable bit
0 : CTS, RTS function is enabled.
1 : CTS, RTS function is disabled.
UARTi receive interrupt mode select bit
0 : Reception interrupt
1 : Reception error interrupt
CLK polarity select bit (This bit is used in the clock synchronous serial I/O mode.)
(Note 2)
0 : At the falling edge of a transfer clock, transmit data is output;
at the rising edge, receive data is input.
When not in transfer, pin CLK’s level is “H”.
1 : At the rising edge of a transfer clock, transmit data is output;
at the falling edge, receive data is input.
When not in transfer, pin CLK’s level is “L”.
Transfer format select bit (This bit is used in the clock synchronous serial I/O mode.)
(Note 2)
0 : LSB (Least Significant Bit) first
1 : MSB (Most Significant Bit) first
7
6
5
4
3
2
1
0
RE
RI
OER
FER
PER
SUM
TI
TE
Transmit enable bit
Transmit buffer empty flag
Receive enable bit
Receive complete flag
Overrun error flag
Framing error flag
(Note 3)
Parity error flag
(Note 3)
Error sum flag
(Note 3)
UART0 transmit/receive control register 0
UART1 transmit/receive control register 0
UART2 transmit/receive control register 0
Address
34
16
3C
16
B4
16
UART0 transmit/receive control register 1
UART1 transmit/receive control register 1
UART2 transmit/receive control register 1
Address
35
16
3D
16
B5
16
CPL
Notes 1:
Valid when the CTS/RTS enable bit (bit 4) = “0”.
2:
Fix these bits to “0” in UART mode or when serial I/O is invalid.
3:
Valid in UART mode.
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