參數(shù)資料
型號(hào)： M37905M8C-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： 16 BIT CMOS MICROCOMPUTER
中文描述： 16位CMOS微機(jī)
文件頁(yè)數(shù)： 30/102頁(yè)
文件大?。?/td> 881K
代理商： M37905M8C-XXXFP
30
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
When a phase-related pulse with a falling edge input to the TAk
OUT
pin is input after the level of TAl
IN
pin changes from
“
H
”
to
“
L
”
, the
count is decremented at the respective rising edge and falling edge
of the TAl
IN
pin and TAl
OUT
pin. When performing this two-phase
pulse signal processing, bits 0 and 4 of timer Aj mode register must
be set to
“
1
”
and bits 1, 2, 3, and 5 must be
“
0
”
. Bits 6 and 7 are ig-
nored. (See Figure 27.) Note that bits 5, 6, and 7 of the up-down reg-
ister 0 (address 44
16
) are the two-phase pulse signal processing
select bits for timers A2, A3, and A4, respectively. Also, bits 5, 6, and
7 of the up-down register 1 (address C4
16
) are the two-phase pulse
signal processing select bits for timers A7, A8, and A9, respectively.
Each timer operates in normal event counter mode when the corre-
sponding bit is
“
0
”
and performs two-phase pulse signal processing
when it is
“
1
”
.
Count is started by setting the count start bit to
“
1
”
. Data write and
read are performed in the same way as for normal event counter
mode. Note that the direction register of the input port must be set to
input mode because two kinds of pulse signals, described above,
are input. Also, there can be no pulse output in this mode.
Fig. 27 Bit configuration of timer Aj mode register when performing
two-phase pulse signal processing in event counter mode
Fig. 25 Two-phase pulse processing operation of timer A2, A3, A7,
A8
Fig. 26 Two-phase pulse processing operation of timers A4 and A9
TAk
OUT
Decre-
ment-
count
Decre-
ment-
count
Decre-
ment-
count
Incre-
ment-
count
Incre-
ment-
count
Incre-
ment-
count
TAk
IN
(k = 2, 3, 7, 8)
Fig. 24 Bit configuration of up-down register
Timer A0 up-down bit
Timer A1 up-down bit
Timer A2 up-down bit
Timer A3 up-down bit
Timer A4 up-down bit
Timer A2 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A3 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A4 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Up-down register 0
Address
44
16
7
6
5
4
3
2
1
0
Timer A5 up-down bit
Timer A6 up-down bit
Timer A7 up-down bit
Timer A8 up-down bit
Timer A9 up-down bit
Timer A7 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A8 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A9 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Up-down register 1
Address
C4
16
7
6
5
4
3
2
1
0
TAl
OUT
TAl
IN
(l = 4, 9)
Decrement-count at each edge
Increment-count at each edge
Decrement-count at each edge
Increment-count at each edge
7
×
6
×
5
0
4
1
3
0
2
0
1
0
0
1
0 1 : Always
“
01
”
in event counter mode
0 1 0 0 : Always
“
0100
”
when processing
two-phase pulse signal
×
×
: Not used in event counter mode
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer A7 mode register
Timer A8 mode register
Timer A9 mode register
Addresses
58
16
59
16
5A
16
C8
16
C9
16
CA
16
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