參數(shù)資料
型號(hào)： M37905M6C-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： DIODE SCHOTTKY DUAL-DUAL SERIES 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-363 3K/REEL
中文描述： 16位CMOS微機(jī)
文件頁(yè)數(shù)： 86/102頁(yè)
文件大?。?/td> 881K
代理商： M37905M6C-XXXFP
86
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
WIT mode
When the WIT instruction is executed with the system clock stop se-
lect bit at WIT (bit 3 of the particular function select register 1 in Fig-
ure 93) being
“
0
”
,
φ
BIU
,
φ
CPU
, and divide clocks Wf
32
and Wf
512
are
inactive with the
“
L
“
state. However, the oscillation circuit, PLL circuit,
input clock fX
IN
, system clock f
sys
,
φ
1
, and peripheral devices
’
clocks
f
1
to f
4096
remain active. Therefore, BIU and CPU are inactive, where
as timers A and B, serial I/O, and the A-D converter, which use the
peripheral devices
’
clocks f
1
to f
4096
, are still active. Note that the
watchdog timer is inactive.
On the other hand, when the WIT instruction is executed with the
system clock stop select bit at WIT being
“
1
”
, the oscillation circuit,
PLL circuit, and input clock fX
IN
are active, while system clock f
sys
,
φ
BIU
,
φ
CPU
, and peripheral devices
’
clocks are inactive. As a result,
the A-D converter and watchdog timer, which use peripheral devices
’
clocks f
1
to f
4096
, Wf
32
and Wf
512
, become inactive. At this time, tim-
ers A and B are active only in the event counter mode, and serial I/O
communication is active only while an external clock is selected. If
the internal peripheral devices are not used in the WIT mode, the lat-
ter is better because the current dissipation is more saved. Note that
the system clock stop select bit at WIT needs to be set to
“
1
”
immedi-
ately before execution of the WIT instruction and cleared to
“
0
”
im-
mediately after the WIT mode is terminated.
The WIT state is terminated by acceptance of an interrupt request,
and then, supply of
φ
BIU
and
φ
CPU
will restart. Since the oscillation
circuit, PLL circuit, and clock input fX
IN
are active in the WIT mode,
an interrupt processing can be executed just after the WIT mode ter-
mination.
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