參數(shù)資料
型號(hào)： M37905M6C-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： DIODE SCHOTTKY DUAL-DUAL SERIES 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-363 3K/REEL
中文描述： 16位CMOS微機(jī)
文件頁(yè)數(shù)： 67/102頁(yè)
文件大小： 881K
代理商： M37905M6C-XXXFP
67
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Figure 74 shows the bit configuration of the comparator function se-
lect register 0 (address DC
16
), and Figure 75 shows that of the com-
parator function select register 1 (address DD
16
). Each of bits 7 to 0
corresponds to its own channel, respectively. Each channel can be
selected as either an A-D converter or a comparator. When the bit is
“0”, the channel corresponding to it functions as a 10-bit or an 8-bit
A-D converter. When the bit is “1”, the channel functions as a com-
parator.
When selecting an A-D converter, an input voltage to a selected ana-
log input pin is A-D converted and the result is stored into one of
these A-D registers.
When selecting a comparator, D-A conversion is performed to the
value of which high-order 8 bits are the value stored in an even ad-
dress of the A-D converter and of which low-order 2 bits are “10
2
.”
Then, this D-A converted value is compared with the voltage sup-
plied to an analog input pin. After the comparison, when the voltage
supplied to an analog input pin is higher, “1” is stored into the com-
parator result register 0 (address DE
16
) shown in Figure 76, or the
comparator result register 1 (Address DF
16
) shown in Figure 77.
When it is lower, “0” is stored into that of these register.
Be sure to perform only read to the A-D register of which channel is
selected as an A-D converter, and perform only write to the A-D reg-
ister of which channel is selected as a comparator. Additionally, do
not write to the comparator function select registers 0, 1 and the A-D
register while an A-D converter or a comparator is operating.
Port direction register’s bits corresponding to pins to be A-D con-
verted must be “0” (input mode) because analog input ports are mul-
tiplexed with ports P7 and P8.
Figure 78 shows the bit configuration of the A-D control register 0
(address 1E
16
), Figure 79 shows that of the A-D control register 1
(address 1F
16
), and Figure 80 shows that of the A-D control register
2 (address DB
16
).
The operation clock of the A-D converter,
φ
AD
, is selected by the fol-
lowing bits: bit 7 of the A-D control register 0 and bit 4 of the A-D con-
trol register 1.
When bit 4 of the A-D control register 1 = “0”,
φ
AD
is selected as fol-
lows:
if bit 7 of the A-D control register 0 = “0”,
φ
AD
= f
2
/4.
if bit 7 of the A-D control register 0 = “1”,
φ
AD
= f
2
/2.
When bit 4 of the A-D control register 1 = “1”,
φ
AD
is selected as fol-
lows:
if bit 7 of the A-D control register 0 = “0”,
φ
AD
= f
2
.
if bit 7 of the A-D control register 0 = “1”,
φ
AD
= f
1
.
Note that the highest frequency,
φ
AD
= f
1
, can be selected only in the
8-bit resolution mode.
φ
AD
during A-D conversion must be 250 kHz or more because the
comparator uses a capacity coupling amplifier.
Bit 3 of A-D control register 1 is used to select whether to regard the
conversion result as 10-bit or as 8-bit data. The conversion result is
regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3
is “0”.
When the conversion result is used as 10-bit data, the low-order 8
bits of the conversion result are stored in the even address of the
corresponding A-D register and the high-order 2 bits are stored in
bits 0 and 1 at the odd address of the corresponding A-D register.
Bits 2 to 7 of the A-D register odd address are “000000
2
” when read.
When the conversion result is used as 8-bit data, the high-order 8
bits of the 10-bit A-D conversion result are stored in even address of
the corresponding A-D register. In this case, the value at the A-D
register’s odd address is “00
16
” when read.
Whether to connect the reference voltage input (V
REF
) with the lad-
der network or not depends on bit 5 of the A-D control register 1. The
V
REF
pin is connected when bit 5 is “0” and is disconnected when bit
5 is “1” (High impedance state).
When A-D or D-A conversion is not performed, current from the V
REF
pin to the ladder network can be cut off by disconnecting ladder net-
work from the V
REF
pin.
Before starting A-D conversion, wait for 1
μ
s or more after clearing
bit 5 to “0”.
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