參數(shù)資料
型號: M37905M6C-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: DIODE SCHOTTKY DUAL-DUAL SERIES 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-363 3K/REEL
中文描述: 16位CMOS微機
文件頁數(shù): 59/102頁
文件大?。?/td> 881K
代理商: M37905M6C-XXXFP
59
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 66 Clock synchronous serial I/O timing
Interrupt request at completion of reception
When the RIk flag changes from
0
to
1
, in other words, when the
receive operation is completed, the interrupt request bit of the
UARTk receive interrupt control register can be set to
1
.
The timing when this interrupt request bit is to be set to
1
can be
selected from the following:
Each reception
When an error occurs at reception
If bit 5 of the UARTk transmit/receive control register 0 (UART re-
ceive interrupt mode select bit) is cleared to
0
, the interrupt request
bit is set to
1
at each reception. If bit 5 is set to
1
, the interrupt re-
quest bit is set to
1
only when an error occurs. (In the clock syn-
chronous serial communication, only when an overrun error occurs,
the interrupt request bit is set to
1
.)
Polarity of transfer clock
In the clock synchronous serial communication, by bit 6 of the UARTj
transmit/receive control register 0 (CPL), the polarity of a transfer
clock can be selected.
As shown in Figure 67, when bit 6 =
0
, the polarity is as follows:
In transmission, transmit data is output at the falling edge of CLK
j
.
In reception, receive data is input at the rising edge of CLK
k
.
When not in transfer, CLK
i
is at
H
level.
When bit 6 =
1
, the polarity is as follows:
In transmission, transmit data is output at the rising edge of CLK
j
.
In reception, receive data is input at the rising edge of CLK
k
.
When not in transfer, CLK
i
is at
L
level.
Transmission
clock
TE
j
1/f
i
×
(n
+
1)
×
2
1/f
i
×
(n
+
1)
×
2
TI
j
CTS
j
Write in transmit buffer register
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
Transmit register
Transmit buffer register
Stopped because TE
j
=
0
CLK
j
T
ENDj
T
X
D
j
T
X
EPTY
j
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