參數(shù)資料
型號： M37754M8C-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
中文描述： 單芯片16位微機的CMOS
文件頁數(shù)： 44/114頁
文件大小： 1116K
代理商： M37754M8C-XXXHP
44
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Additionally, pulse width modulation can be applied for the pulse out-
put port RTP1. Because the timer A2 is used for pulse width modula-
tion, actuate timer A2 in the pulse width modulation mode. When any
bit of pulse output data is “1”, the pulse to which pulse width modula-
tion is applied is output from the pulse output port when the contents
of timer A1 counter become 0000
16
.
Pulse width modulation by timer A2 is applied when setting the pulse
width modulation select bit 0 (bit 4) of waveform output mode regis-
ter to “1”, pulse width modulation select bit 1 (bit 5) to “0,” and the
pulse width modulation data bit of RTP1 (bit 5) of pulse output data
register 0 to “1”.
RTP0
3
, RTP0
2
, RTP0
1
and RTP0
0
can output the contents of pulse
output data register 0 by setting the polarity select bit (bit 3) of wave-
form output mode register. When the polarity select bit is “1”, the re-
versed contents of pulse output data register 0 is output; when that
bit is “0”, the contents of pulse output data register 0 are output as it
is. Figure 52 shows example waveforms in the pulse mode 0.
In ports selecting the pulse mode 0, output of RTP0
3
, RTP0
2
, RTP0
1
and RTP0
0
is controlled by the waveform output control bit 0 (bit 6)
of waveform output mode register; output of RTP1
3
, RTP1
2
, RTP1
1
and RTP1
0
is done by the waveform output control bit 1 (bit 7).
When setting the waveform output control bit to “1”, waveform is out-
put from the corresponding port. When clearing that bit to “0”, wave-
form output from the corresponding port stops, and the port
becomes floating. The waveform output control bits are cleared to “0”
by reset other than clearing with instructions.
Pulse mode 1
This mode divides a pulse output port into 6 bits and 2 bits, and indi-
vidually controls them.
When setting the pulse output mode select bit to “1”, and setting bit 2
to “0” and bits 1 and 0 to “1” of the waveform output select bits, the
following two groups become the pulse output ports:
Six of RTP1
3
, RTP1
2
, RTP1
1
, RTP1
0
, RTP0
3
, RTP0
2
Two of RTP0
1
, RTP0
0
.
Timer A1 controls six of RTP1
3
, RTP1
2
, RTP1
1
, RTP1
0
, RTP0
3
, and
RTP0
2
; timer A0 controls two of RTP0
1
, RTP0
0
.
Additionally, pulse width modulation can be applied for the pulse out-
put ports (RTP1, RTP0
3
, RTP0
2
). The pulse width modulation select
bit 1 (bit 5) of waveform output mode register selects the type of
modulation: the common modulation to six of RTP1
3
, RTP1
2
, RTP1
1
,
RTP1
0
, RTP0
3
and RTP0
2
or the modulation to every two ports of
RTP1
3
and RTP1
2
, RTP1
1
and RTP1
0
, RTP0
3
and RTP0
2
.
When setting that bit to “0”, the common modulation to six ports is
applied; when setting that bit to “1”, the modulation to every two ports
is applied. The timer A2 is used for the common modulation to six
ports; the timers A2, A3 and A4 are used for the modulation to every
two ports. Accordingly, actuate the respective timers in the pulse
width modulation mode. When any bit of pulse output data is “1”, the
pulse to which pulse width modulation is applied is output from the
pulse output port when the contents of timer A1 counter become
0000
16
.
Pulse width modulation by corresponding timers is applied when set-
ting the pulse width modulation select bit 0 of waveform output mode
register to “1” and the corresponding pulse width modulation data
bits (bits 7 to 5) of pulse output data register 0 to “1”.
The polarity select bit (bit 3) of waveform output mode register must
be “0” to select the positive polarity. The other operations are the
same as that of pulse mode 0. Figure 53 shows example waveforms
in the pulse mode 1.
In ports selecting the pulse mode 1, output of RTP0
1
and RTP0
0
is
controlled by the waveform output control bit 0 (bit 6) of waveform
output mode register; output of RTP1
3
, RTP1
2
, RTP1
1
, RTP1
0
,
RTP0
3
and RTP0
2
is done by the waveform output control bit 1
(bit 7).
When setting the waveform output control bit to “1”, waveform is out-
put from the corresponding port. When clearing that bit to “0”, wave-
form output from the corresponding port stops and the port becomes
floating. The waveform output control bits are cleared to “0” by reset
other than clearing with instructions.
(in Fig. 15) is set to “1”, this register’s contents can be
changed from the status after reset (in Fig.76).
Pulse output data register 1 1C
16
RTP1
0
pulse output data bit
RTP1
1
pulse output data bit
RTP1
2
pulse output data bit
RTP1
3
pulse output data bit
Pulse output mode select bit
0 : Pulse mode 0
1 : Pulse mode 1
: Not used in pulse output port mode
7
×
6
×
5
×
4
3
2
1
0
Address
Pulse output data register 0 1D
16
RTP0
0
pulse output data bit
RTP0
1
pulse output data bit
RTP0
2
pulse output data bit
RTP0
3
pulse output data bit
In pulse mode 0
Pulse width modulation data bit of RTP1
In pulse mode 1
Pulse width modulation data bit of
RTP0
3
, RTP0
2
In pulse mode 1
Pulse width modulation data bit of
RTP1
1
, RTP1
0
In pulse mode 1
Pulse width modulation data bit of
RTP1
3
, RTP1
2
7
6
5
4
3
2
1
0
Address
Note :
Only when bit 5 of the particular function select register 1
Fig. 51 Bit configuration of pulse output data registers 1 and 0 in
pulse output port mode
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