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參數(shù)資料
| 型號： | M37736MHLXXXHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁數(shù)： | 37/96頁 |
| 文件大?。?/td> | 1328K |
| 代理商： | M37736MHLXXXHP |
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37
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
0
1
0
TEcontrol register 1
Trasmit enable flag
0 : Receiving is disabled
35
16
Address
UART0 transmit/receive
mode register
7
6
5
4
3
2
1
0
0
0
1
0
0
Address
30
16
001 : Clock synchronous
0 : Internal clock
0 : always “0”
: Not used
Transfer format selection bit
0 : LSB first
1 : MSB first
AAAAAA
(I/O port)
Data output selection bit
0 : CMOS output
1 :
N-channel open-drain output
1 : Disable
CTS
and
RTS
7
6
5
4
3
2
0
1
1
TPM
CPL TxS
CS
1
CS
2
UART0 transmit/receive
control register 0
Clock source selection bits
0 0 : Select f
2
0 1 : Select f
16
1 0 : Select f
64
1 1 : Select f
512
: Not used
CLK polarity selection bit
0 :
In transmitting, transmit data
is output at the CLK's falling
edge. Not in transmitting,
CLK
0
level is “H”.
1 :
In transmitting, transmit data
is output at the CLK0's rising
edge. Not in transmitting,
CLK
0
level is “L”.
Address
34
16
Fig. 45 Bit configuration of UART0 transmit/receive mode register
and UART0 transmit/receive control register 0/1 in the
transmission clock output multiple-selection mode
Receive
Receive starts when the bit 2 (RE
k
flag) of the UART
k
transmit/receive
control register 1 is set to “1”.
The
RTS
k
output level is “H” when the RE
k
flag is “0”, but it is “L” when
the RE
k
flag is “1” and the TI
k
flag is “0”. Furthermore, the
RTS
k
output
level is “H” again when receiving restarts. The TI
k
flag is cleared to
“0” by writing dummy data into the transmission buffer register. When
the
RTS
k
output level is “L”, receiving for the receive register is enabled.
UART2 does not have the
RTS
output function.
When bit 6 (CPL) of the UART
k
transmit/receive control register 0 is
“0”, the contents of the receive register is shifted by 1 bit each time
when the receive clock (CLK
k
) changes from “L” to “H”. When CPL is
“1”, the contents is shifted by 1 bit each time when CLK
k
changes
from “H” to “L”. These shifts are performed simultaneously with the
data reception from the R
X
D
k
pin. When an 8-bit data is received, the
contents of the receive register is transferred to the receive buffer
register and the bit 3 (RI
k
flag) of the UART
k
transmit/receive control
register 1 is set to “1”. In other words, the setting of the RI
k
flag to “1”
indicates that the receive buffer register contains the received data.
When the TI
k
flag goes “0”,
RTS
k
output level goes “L” to indicate that
the next data can be received. When the RI
k
flag changes from “0” to
“1”, the interrupt request bit of the UART
k
receive (transmit/receive in
UART2) interrupt control register is set to “1”. Bit 4 (OER
k
flag) of the
UART
k
transmit/receive control register is set to “1” when the next
data is transferred from the receive register to the receive buffer
register while RI
k
flag is “1”, and the OER
k
flag indicates that the next
data was transferred to the receive buffer register before the contents
of the receive buffer register was read.
The RI
k
flag is cleared to “0” when reading the low-order byte to the
receive buffer, when writing “0” to the RE
k
flag, or when setting to be
a parallel port. The OER
k
flag is cleared to “0” when writing “0” to the
RE
k
flag or when setting to be a parallel port. The FER
k
, PER
k
, and
SUM
k
flags are ineffective in the clock synchronous communication.
The received data in the receive buffer register is read into the data
bus according to the LSB first (beginning at the least significant bit)
when bit 7 (TEM) of the UART
k
transmit/receive control register 0 is
“0” or according to the MSB first (beginning at the most significant
bit) when bit 7 is “1”.
As shown in Figure 36, with clock synchronous serial communication,
data cannot be received unless the transmitter is operating because
the receive clock is created from the transmission clock. Therefore,
the transmitter must be operating even when there is no data to be
sent from UART
k
to UART
j
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37736EHBXXXGP | PROM VERSION OF M37736MHBXXXGP(MICROCOMPUTERS) |
| M37736MHBXXXGP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37753FFCFP | SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37753FFCHP | SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37754M8C-XXXGP | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37753FFCFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37753FFCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37753M6C-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37753M6C-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37753M8C-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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