參數(shù)資料
型號(hào)： M37736MHLXXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 36/96頁
文件大?。?/td> 1328K
代理商： M37736MHLXXXHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
36
transmit/receive mode register and the UART0 transmit/receive
control register 0/1 in the transmission clock output multiple-selection
mode. Furthermore, Table 6 shows the function of bits 5 and 4
(Transmission clock output pin selection bits, TC
1
and TC
0
) of the
serial transmit control register. As shown in Table 5, the transmission
clock is output from the CLK
0
, CLKS
0
, or CLKS
1
pin depending on
TC
1
, TC
0
. Do not change the value of TC
1
and TC
0
during transferring.
The transmission clock polarity also depends on bit 6 (CPL) of the
UART0 transmit/receive control register 0.
When the transmission register becomes empty after its contents
has been transmitted, data is automatically transferred from the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied. When bit 2 of the UART
j
transmit/receive control register 0 is “1”,
CTS
j
input is ignored and
transmission start is controlled only by the TE
j
flag and TI
j
flag. Once
transmission has started, the TE
j
flag, TI
j
flag, and
CTS
j
signals are
ignored until data transmission completes. Therefore, transmission
is not interrupt even when
CTS
j
input is changed to “H” during
transmission.
___
As shown in Figure 42,
CTS
j
and flags TE
j
and TI
j
, which indicate the
transmission start condition, are checked while the T
ENDj
signal is
“H”. Therefore, data can be transmitted continuously when the next
transmission data is written in the transmission buffer register and
the TI
j
flag is cleared to “0” before the T
ENDj
signal level becomes H”.
The bit 3 (T
X
EPTY
j
flag) of the UART
j
transmit/receive control register
0 changes to “1” at the next cycle after the T
ENDj
signal level becomes
“H”. Furthermore, the TxEPTY
j
flag changes to “0” when transmission
starts. Therefore, this flag can be used to determine whether data
transmission has been completed.
When the TI
j
flag changes from “0” to “1”, the interrupt request bit in
the UART
j
transmission (transmit/receive in UART2) interrupt control
register is set to “1”.
Since UART0 has three output pins (CLK
0
, CLKS
0
, and CLKS
1
) for
the transmission clock, the user can select one from these pins when
using the internal clock. Accordingly, data can be transmitted to three
external receive devices which will not receive data at the same time.
Figure 43 shows the extrnal connection diagram example.
To select the transmission clock output multiple-selection mode, it is
necessary to set bits 5 and 4 of the serial transmit control register. In
addition, it is necessary to select the internal clock, to disable
CTS
and
RTS
, and disable reception, with the UART0 transmit/receive
mode register and the UART0 transmit/receive control register 0/1.
Figure 44 shows the bit configuration of the serial transmit control
register and Figure 45 shows the bit configuration of the UART0
Fig. 44 Bit configuration of serial transmit control register
Table 6. Relationship between transmission clock output pin selection
bits and pin functions
Transmission clock
output pin selection bits
TC
1
TC
0
CLK
0
0
0
1
1
0
1
0
1
CLK
0
CLK
0
“H”
“H”
R
X
D
0
“H” (Note2)
CLKS
0
“H” (Note2)
P8/
CTS
0
/
RTS
0
P8
0
P8
0
CLKS
1
P8
1
P8
2
R
X
D
0
CLKS
0
___ ___
CTS
0
RTS
0
CLKS
1
Notes 1.
In this table, the CLK polarity selection bit (CPL) is “0”.
When CPL is “1”, “H” in this table becomes “L”. The polarity
of CLK
0
, CLKS
0
, or CLKS
1
also depends on CPL.
2.
When bit 2 of the port P8 direction register is “1”, “H” is
output. When this bit is “0”, floating is entered.
DIN
CLK
DIN
CLK
DIN
CLK
T
X
D
0
CLKS
1
CLKS
0
CLK
0
UART 0
Note.
Clock synchronous serial I/O communication and internal clock are used.
This connection is applied only in transmission mode.
7
5
4
3
2
1
0
6
Serial transmit
control register
Transmission clock output pin selection bits
0 0 : Normal mode
(Clock is output only from CLK
0
)
0 1 : Multiple clocks are specified
(Clock is output from CLK
0
)
1 0 : Multiple clocks are specified
(Clock is output from CLKS
0
)
1 1 : Multiple clocks are specified
(Clock is output from CLKS
1
)
TC
1
TC
0
Adress
6E
16
Fig. 43 External connection diagram example in the transmission clock output multiple-selection mode
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